#include "message_deal.h"



// #include <qscreen.h>
// #include <QDirIterator>

// #include <QDateTime>
// #include <QString>
#include <sys/time.h>
#include <stdio.h>

#include <memory.h>
#include <stdio.h>
#include <unistd.h>



#include "../fpga_manage.h"



#include "../../global/BxGlobal.h"


//static Ouint8 fileBuf_onbon[5*1024*1024];
static Ouint8 flag_onbon = 0 ;
static Ouint32 len_onbon = 0 ;
static FILE* file_onbon = NULL;


Ouint8 g_4G_RAM[256];

//static int app_value = 0;


message_deal::message_deal()
{
    rcv_state = PHY_R_INITIAL_STATE;
}


message_deal::~message_deal()
{
    rcv_state = PHY_R_INITIAL_STATE;
}




/*
 *
 * @param
 * @return
 */
Ouint32 message_deal::write_ram(Ouint8 *Rcv)
{
    Ouint16 src_addr = MCU_DEFAULT_ADDR;
    Ouint32 ram_addr ,start_addr;
    Ouint8 sel_fpga = FPGA_MASTER_VBYONE1;
    Ouint8 ram_num,len_num;
    Ouint16 len ;
    Ouint32 /*ret,*/i;
    Ouint8 valid = 0;
    Ouint8 *p_mcu_ram_back_eth_para = fpga_manage::p_fpga_manage->MCU_RAM_ETH_BACK_PARA_func[FPGA_MASTER_VBYONE1];

    src_addr = Rcv[FRAME_DST_ADDR_L] | Rcv[FRAME_DST_ADDR_H] << 8 ;
    ram_addr = Rcv[FRAME_CMD+1] | (Rcv[FRAME_CMD+2] <<8) | (Rcv[FRAME_CMD+3]<<16) | (Rcv[FRAME_CMD+4]<<24) ;
    len = Rcv[FRAME_CMD+5] | (Rcv[FRAME_CMD+6] <<8) ;

    if(src_addr == MCU_DEFAULT_ADDR || src_addr == MCU_DEFAULT_ADDR1){

        //dsp ram para
        if(ram_addr < 0x1000) {

            //Rcv[FRAME_CMD + 1] = OvpRamPara::OvpRamParaDeal(&Rcv[FRAME_CMD+9],len,ram_addr) ;
        }else if(ram_addr < 0x11000){

            //Rcv[FRAME_CMD + 1] = OvpRamPara::OvpModeUserRamParaDeal(&Rcv[FRAME_CMD+9],len,ram_addr) ;
        }else if((ram_addr >= 0xA1000000)&&(ram_addr+len <= 0xA1000100)){

            for(i = 0;i < len; i++){
                g_4G_RAM[i] = Rcv[FRAME_CMD+9+i];
            }

            Rcv[FRAME_CMD + 1] = CMD_ACK_NOERR;
        }/*else if(ram_addr == 0x99999999){
            //reg
            //data
            //fpga_manage::write_fpga_ram(fpga_manage::MCU_RAM_RX_func[sel_fpga],ram_addr,len,RX_RAM_12+len_num-1,sel_fpga);

            fpga_manage::p_fpga_manage->write_LCD_register(Rcv[FRAME_CMD+7] , &Rcv[FRAME_CMD+8], FPGA_MASTER_VBYONE2 , (Ouint8)len) ;
            //fpga_manage::p_fpga_manage->write_LCD_register(Rcv[FRAME_CMD+7] , &Rcv[FRAME_CMD+8], FPGA_MASTER_VBYONE2 , (Ouint8)len) ;

        }*/




    }else{
        //default maybe fpga
        if(Rcv[FRAME_CONTROL_CLASS]==CONTROL_CLASS_TXC){
            if((Rcv[FRAME_NETPORT]>=1)&&(Rcv[FRAME_NETPORT]<=2)){
                sel_fpga = Rcv[FRAME_NETPORT]-1;
                valid = 0;
            }else{
                sel_fpga = FPGA_MASTER_VBYONE1;
                valid=1;
            }
        }

        ram_num = Rcv[4+FRAME_CMD] & 0x0f;
        len_num = (Rcv[2+FRAME_CMD]>>4) & 0x0f;//!<获取网口序号
        start_addr = ram_addr & 0x00ffffff;

        if((ram_num == 0) && (start_addr >= 0x800)){
            ram_num = 6;
            start_addr = start_addr - 0x800;
        }

        if(ram_num == 1){
            start_addr = start_addr & 0xffff0fff;//!<该位为网口序号，算地址时不能算上
        }

        if(ram_num == 2){
            start_addr = start_addr & 0xffff0fff;//!<该位为网口序号，算地址时不能算上
        }

        if((sel_fpga<=1)&&((len + start_addr) <= RAM_MAX_LEN)){//!<数据溢出
            switch(ram_num){
                case 0:{
//                    Ouint16 value;
//                    Ouint16 value1;
                    for(i=0;i<len;i++){
                        fpga_manage::MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = Rcv[9+i+FRAME_CMD];
                    }
                    p_mcu_ram_back_eth_para = fpga_manage::p_fpga_manage->MCU_RAM_ETH_BACK_PARA_func[sel_fpga];
                    for(i=0;i<len;i++){
                        if(ram_addr+i==ETH_LCD_X || ram_addr+i==ETH_LCD_X + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH_LCD_X+ram_addr+i-ETH_LCD_X]=fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }else if(ram_addr+i==ETH_LCD_Y || ram_addr+i==ETH_LCD_Y + 1){
                            p_mcu_ram_back_eth_para[MCU_BAKC_ETH_LCD_Y+ram_addr+i-ETH_LCD_Y]=fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }
                        if(ram_addr+i==ETH_LCD_W || ram_addr+i==ETH_LCD_W + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH_LCD_W+ram_addr+i-ETH_LCD_W]=fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }else if(ram_addr+i==ETH_LCD_H || ram_addr+i==ETH_LCD_H + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH_LCD_H+ram_addr+i-ETH_LCD_H]=fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }else if(ram_addr+i==ETH0_X || ram_addr+i==ETH0_X + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH0_X+ram_addr+i-ETH0_X] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }else if(ram_addr+i==ETH0_Y || ram_addr+i==ETH1_Y + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH0_Y+ram_addr+i-ETH0_Y] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }else if(ram_addr+i==ETH1_X || ram_addr+i==ETH1_X + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH1_X+ram_addr+i-ETH1_X] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }else if(ram_addr+i==ETH1_Y || ram_addr+i==ETH1_Y + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH1_Y+ram_addr+i-ETH1_Y] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }else if(ram_addr+i==ETH2_X || ram_addr+i==ETH2_X + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH2_X+ram_addr+i-ETH2_X] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }else if(ram_addr+i==ETH2_Y || ram_addr+i==ETH2_Y + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH2_Y+ram_addr+i-ETH2_Y] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }else if(ram_addr+i==ETH3_X || ram_addr+i==ETH3_X + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH3_X+ram_addr+i-ETH3_X] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }else if(ram_addr+i==ETH3_Y || ram_addr+i==ETH3_Y + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH3_Y+ram_addr+i-ETH3_Y] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }else if(ram_addr+i==ETH4_X || ram_addr+i==ETH4_X + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH4_X+ram_addr+i-ETH4_X] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }else if(ram_addr+i==ETH4_Y || ram_addr+i==ETH4_Y + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH4_Y+ram_addr+i-ETH4_Y] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }else if(ram_addr+i==ETH5_X || ram_addr+i==ETH5_X + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH5_X+ram_addr+i-ETH5_X] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }else if(ram_addr+i==ETH5_Y || ram_addr+i==ETH5_Y + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH5_Y+ram_addr+i-ETH5_Y] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }else if(ram_addr+i==ETH6_X || ram_addr+i==ETH6_X + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH6_X+ram_addr+i-ETH6_X] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }else if(ram_addr+i==ETH6_Y || ram_addr+i==ETH6_Y + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH6_Y+ram_addr+i-ETH6_Y] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }else if(ram_addr+i==ETH7_X || ram_addr+i==ETH7_X + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH7_X+ram_addr+i-ETH7_X] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }else if(ram_addr+i==ETH7_Y || ram_addr+i==ETH7_Y + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH7_Y+ram_addr+i-ETH7_Y] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }else if(ram_addr+i==ETH8_X || ram_addr+i==ETH8_X + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH8_X+ram_addr+i-ETH8_X] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }else if(ram_addr+i==ETH8_Y || ram_addr+i==ETH8_Y + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH8_Y+ram_addr+i-ETH8_Y] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }else if(ram_addr+i==ETH9_X || ram_addr+i==ETH9_X + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH9_X+ram_addr+i-ETH9_X] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }else if(ram_addr+i==ETH9_Y || ram_addr+i==ETH9_Y + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH9_Y+ram_addr+i-ETH9_Y] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }else if(ram_addr+i==ETH10_X || ram_addr+i==ETH10_X + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH10_X+ram_addr+i-ETH10_X] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }else if(ram_addr+i==ETH10_Y || ram_addr+i==ETH10_Y + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH10_Y+ram_addr+i-ETH10_Y] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }else if(ram_addr+i==ETH11_X || ram_addr+i==ETH11_X + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH11_X+ram_addr+i-ETH11_X] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }else if(ram_addr+i==ETH11_Y || ram_addr+i==ETH11_Y + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH11_Y+ram_addr+i-ETH11_Y] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }else if(ram_addr+i==ETH12_X || ram_addr+i==ETH12_X + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH12_X+ram_addr+i-ETH12_X] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }else if(ram_addr+i==ETH12_Y || ram_addr+i==ETH12_Y + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH12_Y+ram_addr+i-ETH12_Y] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }else if(ram_addr+i==ETH13_X || ram_addr+i==ETH13_X + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH13_X+ram_addr+i-ETH13_X] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }else if(ram_addr+i==ETH13_Y || ram_addr+i==ETH13_Y + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH13_Y+ram_addr+i-ETH13_Y] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }else if(ram_addr+i==ETH14_X || ram_addr+i==ETH14_X + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH14_X+ram_addr+i-ETH14_X] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }else if(ram_addr+i==ETH14_Y || ram_addr+i==ETH14_Y + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH14_Y+ram_addr+i-ETH14_Y] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }else if(ram_addr+i==ETH15_X || ram_addr+i==ETH15_X + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH15_X+ram_addr+i-ETH15_X] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }else if(ram_addr+i==ETH15_Y || ram_addr+i==ETH15_Y + 1){
                            p_mcu_ram_back_eth_para[MCU_BACK_ETH15_Y+ram_addr+i-ETH15_Y] =fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }
                    }

                    //写入FPGA内部
                    fpga_manage::write_fpga_ram(&fpga_manage::MCU_RAM_PARA_func[sel_fpga][ram_addr],ram_addr,len,PARA_RAM,sel_fpga);
                    //write_to_register(0x02,0x01,0x01);//更新寄存器 [原来M1X 没有执行此命令]
                    #if (defined OUTPUT_BOARD_2)
                     if(valid==1){
                        //要求两个TXC同步进行操作  操作从主机
                         for(i=0;i<len;i++){
                           fpga_manage:: MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i] = Rcv[9+i+FRAME_CMD];
                        }

                         p_mcu_ram_back_eth_para = fpga_manage::p_fpga_manage->MCU_RAM_ETH_BACK_PARA_func[FPGA_MASTER_VBYONE2];
                         for(i=0;i<len;i++){
                             if(ram_addr+i==ETH_LCD_X || ram_addr+i==ETH_LCD_X + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH_LCD_X+ram_addr+i-ETH_LCD_X]=fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }else if(ram_addr+i==ETH_LCD_Y || ram_addr+i==ETH_LCD_Y + 1){
                                 p_mcu_ram_back_eth_para[MCU_BAKC_ETH_LCD_Y+ram_addr+i-ETH_LCD_Y]=fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }
                             if(ram_addr+i==ETH_LCD_W || ram_addr+i==ETH_LCD_W + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH_LCD_W+ram_addr+i-ETH_LCD_W]=fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }else if(ram_addr+i==ETH_LCD_H || ram_addr+i==ETH_LCD_H + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH_LCD_H+ram_addr+i-ETH_LCD_H]=fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }else if(ram_addr+i==ETH0_X || ram_addr+i==ETH0_X + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH0_X+ram_addr+i-ETH0_X] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }else if(ram_addr+i==ETH0_Y || ram_addr+i==ETH1_Y + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH0_Y+ram_addr+i-ETH0_Y] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }else if(ram_addr+i==ETH1_X || ram_addr+i==ETH1_X + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH1_X+ram_addr+i-ETH1_X] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }else if(ram_addr+i==ETH1_Y || ram_addr+i==ETH1_Y + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH1_Y+ram_addr+i-ETH1_Y] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }else if(ram_addr+i==ETH2_X || ram_addr+i==ETH2_X + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH2_X+ram_addr+i-ETH2_X] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }else if(ram_addr+i==ETH2_Y || ram_addr+i==ETH2_Y + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH2_Y+ram_addr+i-ETH2_Y] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }else if(ram_addr+i==ETH3_X || ram_addr+i==ETH3_X + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH3_X+ram_addr+i-ETH3_X] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }else if(ram_addr+i==ETH3_Y || ram_addr+i==ETH3_Y + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH3_Y+ram_addr+i-ETH3_Y] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }else if(ram_addr+i==ETH4_X || ram_addr+i==ETH4_X + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH4_X+ram_addr+i-ETH4_X] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }else if(ram_addr+i==ETH4_Y || ram_addr+i==ETH4_Y + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH4_Y+ram_addr+i-ETH4_Y] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }else if(ram_addr+i==ETH5_X || ram_addr+i==ETH5_X + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH5_X+ram_addr+i-ETH5_X] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }else if(ram_addr+i==ETH5_Y || ram_addr+i==ETH5_Y + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH5_Y+ram_addr+i-ETH5_Y] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }else if(ram_addr+i==ETH6_X || ram_addr+i==ETH6_X + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH6_X+ram_addr+i-ETH6_X] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }else if(ram_addr+i==ETH6_Y || ram_addr+i==ETH6_Y + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH6_Y+ram_addr+i-ETH6_Y] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }else if(ram_addr+i==ETH7_X || ram_addr+i==ETH7_X + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH7_X+ram_addr+i-ETH7_X] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }else if(ram_addr+i==ETH7_Y || ram_addr+i==ETH7_Y + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH7_Y+ram_addr+i-ETH7_Y] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }else if(ram_addr+i==ETH8_X || ram_addr+i==ETH8_X + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH8_X+ram_addr+i-ETH8_X] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }else if(ram_addr+i==ETH8_Y || ram_addr+i==ETH8_Y + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH8_Y+ram_addr+i-ETH8_Y] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }else if(ram_addr+i==ETH9_X || ram_addr+i==ETH9_X + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH9_X+ram_addr+i-ETH9_X] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }else if(ram_addr+i==ETH9_Y || ram_addr+i==ETH9_Y + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH9_Y+ram_addr+i-ETH9_Y] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }else if(ram_addr+i==ETH10_X || ram_addr+i==ETH10_X + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH10_X+ram_addr+i-ETH10_X] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }else if(ram_addr+i==ETH10_Y || ram_addr+i==ETH10_Y + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH10_Y+ram_addr+i-ETH10_Y] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }else if(ram_addr+i==ETH11_X || ram_addr+i==ETH11_X + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH11_X+ram_addr+i-ETH11_X] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }else if(ram_addr+i==ETH11_Y || ram_addr+i==ETH11_Y + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH11_Y+ram_addr+i-ETH11_Y] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }else if(ram_addr+i==ETH12_X || ram_addr+i==ETH12_X + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH12_X+ram_addr+i-ETH12_X] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }else if(ram_addr+i==ETH12_Y || ram_addr+i==ETH12_Y + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH12_Y+ram_addr+i-ETH12_Y] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }else if(ram_addr+i==ETH13_X || ram_addr+i==ETH13_X + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH13_X+ram_addr+i-ETH13_X] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }else if(ram_addr+i==ETH13_Y || ram_addr+i==ETH13_Y + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH13_Y+ram_addr+i-ETH13_Y] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }else if(ram_addr+i==ETH14_X || ram_addr+i==ETH14_X + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH14_X+ram_addr+i-ETH14_X] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }else if(ram_addr+i==ETH14_Y || ram_addr+i==ETH14_Y + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH14_Y+ram_addr+i-ETH14_Y] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }else if(ram_addr+i==ETH15_X || ram_addr+i==ETH15_X + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH15_X+ram_addr+i-ETH15_X] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }else if(ram_addr+i==ETH15_Y || ram_addr+i==ETH15_Y + 1){
                                 p_mcu_ram_back_eth_para[MCU_BACK_ETH15_Y+ram_addr+i-ETH15_Y] =fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr+i];
                             }
                        }

                        //写入FPGA内部
                       fpga_manage:: write_fpga_ram(&fpga_manage::MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ram_addr],ram_addr,len,PARA_RAM,FPGA_MASTER_VBYONE2);
                     }
                     #endif

                    //更新一下LCD界面中有关网口坐标参数
                    break;
                }
                case 1:{      //!<网口发送接收部分

                    switch(len_num){
                        case 1:
                        case 3:
                        case 5:
                        case 7:
                        case 9:
                        case 11:
                        case 13:
                        case 15:
                        for(i=0;i<len;i++){
                            fpga_manage::MCU_RAM_RX_func[sel_fpga][i] = Rcv[9+i+FRAME_CMD];
                        }
                        //写入FPGA内部
                        fpga_manage::write_fpga_ram(fpga_manage::MCU_RAM_RX_func[sel_fpga],ram_addr,len,RX_RAM_12+len_num-1,sel_fpga);

                        #if (defined OUTPUT_BOARD_2)
                        if(valid==1){
                            for(i=0;i<len;i++){
                                fpga_manage::MCU_RAM_RX_func[FPGA_MASTER_VBYONE2][i] = Rcv[9+i+FRAME_CMD];
                            }
                            //写入FPGA内部
                            fpga_manage::write_fpga_ram(fpga_manage::MCU_RAM_RX_func[FPGA_MASTER_VBYONE2],ram_addr,len,RX_RAM_12+len_num-1,FPGA_MASTER_VBYONE2);
                        }
                        #endif

                        break;
                        case 2:
                        case 4:
                        case 6:
                        case 8:
                        case 10:
                        case 12:
                        case 14:
                        case 16:
                        for(i=0;i<len;i++){
                            fpga_manage::MCU_RAM_TX_func[sel_fpga][i] = Rcv[9+i+FRAME_CMD];
                        }
                        //写入FPGA内部
                        fpga_manage::write_fpga_ram(fpga_manage::MCU_RAM_TX_func[sel_fpga],ram_addr,len,TX_RAM_12+len_num-2,sel_fpga);

                        #if (defined OUTPUT_BOARD_2)
                        if(valid==1){
                            for(i=0;i<len;i++){
                                fpga_manage::MCU_RAM_TX_func[FPGA_MASTER_VBYONE1][i] = Rcv[9+i+FRAME_CMD];
                            }
                            //写入FPGA内部
                            fpga_manage::write_fpga_ram(fpga_manage::MCU_RAM_TX_func[FPGA_MASTER_VBYONE1],ram_addr,len,TX_RAM_12+len_num-2,FPGA_MASTER_VBYONE2);
                        }
                        #endif
                        break;

                        default:
                        break;
                    }
                    break;
                }
                case 2:{      //!<保留
                switch(len_num){
                case 0:
                    for(i=0;i<len;i++){
                        fpga_manage::MCU_RAM_DEFAULT[i] = Rcv[9+i+FRAME_CMD];
                    }
                    //写入FPGA内部
                    fpga_manage::write_fpga_ram(fpga_manage::MCU_RAM_DEFAULT,ram_addr,len,RECEIVED_RAM,sel_fpga);

                    #if (defined OUTPUT_BOARD_2)
                    if(valid==1){
                        //写入FPGA内部
                        fpga_manage::write_fpga_ram(fpga_manage::MCU_RAM_DEFAULT,ram_addr,len,RECEIVED_RAM,FPGA_MASTER_VBYONE2);
                    }
                    #endif
                    break;
                case 1:
                case 2:
                case 3:
                case 4:
                case 5:
                case 6:
                case 7:
                case 8:
                case 9:
                case 10:
                case 11:
                case 12:
                case 13:
                case 14:
                case 15:
                case 16:
                    for(i=0;i<len;i++){
                        fpga_manage::MCU_RAM_ZOOM[i] = Rcv[9+i+FRAME_CMD];
                    }
                    //写入FPGA内部
                    fpga_manage::write_fpga_ram(fpga_manage::MCU_RAM_ZOOM,ram_addr,len,LCD0_RAM_H+len_num-1,sel_fpga);

                    #if (defined OUTPUT_BOARD_2)
                    if(valid==1){
                        //写入FPGA内部
                        fpga_manage::write_fpga_ram(fpga_manage::MCU_RAM_ZOOM,ram_addr,len,LCD0_RAM_H+len_num-1,FPGA_MASTER_VBYONE2);
                    }
                    #endif
                    break;
                }

                    break;
                }
                case 5:{      //!<扩展命令
                    for(i=0;i<len;i++){
                        fpga_manage::MCU_RAM_CMD[i] = Rcv[9+i+FRAME_CMD];
                    }
                    break;
                }
                case 4:{
                    for(i=0;i<len;i++){
                        fpga_manage::MCU_RAM_TX_func[sel_fpga][i] = Rcv[9+i+FRAME_CMD];
                    }
                  //写入FPGA内部
                  fpga_manage::write_fpga_ram(fpga_manage::MCU_RAM_TX_func[sel_fpga],ram_addr,len,CRC_RAM,sel_fpga);

                  #if (defined OUTPUT_BOARD_2)
                  if(valid==1){
                      for(i=0;i<len;i++){
                          fpga_manage::MCU_RAM_TX_func[FPGA_MASTER_VBYONE2][i] = Rcv[9+i+FRAME_CMD];
                      }
                    //写入FPGA内部
                    fpga_manage::write_fpga_ram(fpga_manage::MCU_RAM_TX_func[FPGA_MASTER_VBYONE2],ram_addr,len,CRC_RAM,FPGA_MASTER_VBYONE2);
                  }
                #endif
                  break;
                }

                case 6:{
                    for(i=0;i<len;i++){
                        fpga_manage::MCU_RAM_EXTEND[start_addr+i] = Rcv[9+i+FRAME_CMD];
                    }

                    Utils::_fpga_multicast_mutex.lock();
                    fpga_manage::p_fpga_manage->set_fpga_multicast_mode =false;// (bool)fpga_manage::MCU_RAM_EXTEND[0x100] ;
                    fpga_manage::p_fpga_manage->fpga_multicast_net = fpga_manage::MCU_RAM_EXTEND[0x101]|(fpga_manage::MCU_RAM_EXTEND[0x102]<<8)|\
                                                                    (fpga_manage::MCU_RAM_EXTEND[0x103]<<16)|(fpga_manage::MCU_RAM_EXTEND[0x104]<<24);

                    if(fpga_manage::p_fpga_manage->set_fpga_multicast_mode==false){
                        fpga_manage::MCU_RAM_EXTEND[0x31] &= 0xBF;
                    }else{
                        fpga_manage::MCU_RAM_EXTEND[0x31] |= 0x40;

                    }
                    Utils::_fpga_multicast_mutex.unlock();

                    break;
                }
                default:
                break;

            }
            Rcv[FRAME_CMD + 1] = CMD_ACK_NOERR ;
        }else{
            Rcv[FRAME_CMD + 1] = CMD_NACK_EXECUTION ;
        }
    }

    return 1;

}



/*
 *
 * @param
 * @return
 */
Ouint32 message_deal::read_ram(Ouint8 *Rcv)
{
    Ouint16 i;
//    Ouint8* ram_p;
    Ouint16 src_addr = MCU_DEFAULT_ADDR;
    Ouint32 ram_addr ,start_addr;
    Ouint8 sel_fpga = FPGA_MASTER_VBYONE1;
    Ouint8 ram_num,len_num;
    Ouint16 len ;
    Ouint16 tem_data;
//    Ouint32 ret;
//    Ouint8 valid = 0;
    Ouint8 user_mode_index ;
    //Ouint8  flash_uid[16] = {0};
    Ouint8 *p_mcu_ram_back_eth_para = fpga_manage::p_fpga_manage->MCU_RAM_ETH_BACK_PARA_func[FPGA_MASTER_VBYONE1];

    src_addr = Rcv[FRAME_DST_ADDR_L] | Rcv[FRAME_DST_ADDR_H] << 8 ;
    ram_addr = (Rcv[4+FRAME_CMD]<<24)|(Rcv[3+FRAME_CMD]<<16)|(Rcv[2+FRAME_CMD]<<8)|Rcv[1+FRAME_CMD];
    len = (Rcv[6+FRAME_CMD]<<8)|Rcv[5+FRAME_CMD];

    if(src_addr == MCU_DEFAULT_ADDR || src_addr == MCU_DEFAULT_ADDR1){

        for(i=0;i<len;i++){
            //about LCD descrpe
            if((i+ram_addr >= RAM_LIST_LCD_SCREEN_DESCRIPE)&&(i+ram_addr < RAM_LIST_LCD_SCREEN_DESCRIPE + 0x80 )) {


            }else if((i+ram_addr >= RAM_LIST_LCD_SCREEN_DATA)&&(i+ram_addr < RAM_LIST_LCD_SCREEN_DATA + 2*1024*1024 )){

            }else if( (i+ram_addr >= RAM_LIST_INPUT_DESCROPTE)&&(i+ram_addr < RAM_LIST_INPUT_DESCROPTE + 40 )  ) {
                //input descripute
                if(  i+ram_addr == RAM_LIST_INPUT_DESCROPTE   ){
                    #if (defined INPUT_SOURCE_TYPE0_NUM4)
                    Rcv[2+i+FRAME_CMD] = 0x03 ;
                    #else
                    Rcv[2+i+FRAME_CMD] = 0x06 ;
                    #endif

                }else   if(  i+ram_addr == RAM_LIST_INPUT_DESCROPTE +1   ){
                    #ifdef OVP_G32_IN_V17
                    Rcv[2+i+FRAME_CMD] = 0x09 ;
                    #elif (defined INPUT_SOURCE_TYPE0_NUM4)
                    Rcv[2+i+FRAME_CMD] = 0x09 ;
                    #else
                    Rcv[2+i+FRAME_CMD] = 0x03 ;
                    #endif

                }else   if(  i+ram_addr == RAM_LIST_INPUT_DESCROPTE +2   ){
                    Rcv[2+i+FRAME_CMD] = 0x09 ;//0x02 ;

                }else   if(  i+ram_addr == RAM_LIST_INPUT_DESCROPTE +3   ){
                    #if (defined INPUT_SOURCE_TYPE0_NUM4)
                    Rcv[2+i+FRAME_CMD] = 0x08 ;
                    #else
                    Rcv[2+i+FRAME_CMD] = 0x09 ;//0x02 ;
                    #endif

                }else   if(  i+ram_addr == RAM_LIST_INPUT_DESCROPTE +4   ){
                    #if (defined INPUT_SOURCE_TYPE0_NUM4)
                    Rcv[2+i+FRAME_CMD] = 0x00 ;
                    #else
                    Rcv[2+i+FRAME_CMD] = 0x08 ;
                    #endif

                }else   if(  i+ram_addr == RAM_LIST_INPUT_DESCROPTE +5   ){
                #ifdef OVP_G32_IN_V17
                    Rcv[2+i+FRAME_CMD] = 0x01 ;
                #elif (defined INPUT_SOURCE_TYPE0_NUM4)
                Rcv[2+i+FRAME_CMD] = 0x00 ;
                #else
                    Rcv[2+i+FRAME_CMD] = 0x08 ;
                #endif

                }else{
                    Rcv[2+i+FRAME_CMD] = 0x00 ;
                }


            }else if( (i+ram_addr >= RAM_LIST_MCU_FUN)&&(i+ram_addr < RAM_LIST_MCU_FUN + 0x400 )    ) {
                //mcu ram fun

            }else if( (i+ram_addr >= RAM_LIST_USER_MODE_START)&&(i+ram_addr < RAM_LIST_USER_MODE_END ) ){

            }else if(  (i+ram_addr >= RAM_LIST_DEVICE_INFO_ADDR)&&(i+ram_addr < RAM_LIST_DEVICE_INFO_ADDR + 0x400 ) ){

            }else if(  (i+ram_addr >= RAM_LIST_331_DUMP_START)&&(i+ram_addr < RAM_LIST_331_DUMP_END )) {

                //c331_manage::p_c331_manage->p_c331_drv->read_C331(c331_manage::p_c331_manage->c331_fd,0xB20801,0);


            }else if( (i+ram_addr >= RAM_LIST_COMMUNITE_STATUS_START)&&(i+ram_addr < RAM_LIST_COMMUNITE_STATUS_END )){
                //Rcv[2+i+FRAME_CMD] = OvpRamPara::p_ovprampara_config->device_communite_status[i+ram_addr-RAM_LIST_COMMUNITE_STATUS_START] ;

            }else if((ram_addr+i >= 0xA1000000)&&(ram_addr+i <= 0xA1000100)){

                //Rcv[2+i+FRAME_CMD] = g_4G_RAM[i];
            }else if( (ram_addr+i >= RAM_LIST_OTHER_CHIP_VER)&&(ram_addr+i < RAM_LIST_OTHER_CHIP_VER + 1024)){
                Rcv[2+i+FRAME_CMD] = 0x00;
            }
            else if((ram_addr+i>=0xA0000000)&&(ram_addr+i<=0xA0000FFF)){  

                Rcv[2+i+FRAME_CMD] = 0x00;

            }
            else{
                //Rcv[2+i+FRAME_CMD] = OvpRamPara::p_ovprampara_config->ovp_ram.ovpG3ram0[i+ram_addr] ;

            }
        }

//        BX_printf("\n read ram  over \n ") ;

        Rcv[1+FRAME_CMD] = 0x00 ;

    }else{

        //default maybe fpga
        if(Rcv[FRAME_CONTROL_CLASS]==CONTROL_CLASS_TXC){
            if((Rcv[FRAME_NETPORT]>=1)&&(Rcv[FRAME_NETPORT]<=2)){
                sel_fpga = Rcv[FRAME_NETPORT]-1;
//                valid = 0;
            }else{
                sel_fpga = FPGA_MASTER_VBYONE1;
//                valid=1;
            }
        }


        ram_num = Rcv[4+FRAME_CMD] & 0x0f;
        len_num = (Rcv[2+FRAME_CMD]>>4) & 0x0f;//!<获取网口序号
        //start_addr = ram_addr & 0x00ffffff;
        start_addr = ram_addr & 0x00000fff;

        if((ram_num == 0) && (start_addr >= 0x800)){
            ram_num = 6;
            start_addr = start_addr - 0x800;
        }

        if(ram_num == 1){
            start_addr = start_addr & 0xffff0fff;//!<该位为网口序号，算地址时不能算上
        }

        if(ram_num == 2){
            start_addr = start_addr & 0xffff0fff;//!<该位为网口序号，算地址时不能算上
        }

        if((len + start_addr) <= RAM_MAX_LEN){//!<数据溢出
            Rcv[1+FRAME_CMD] = CMD_ACK_NOERR;
            switch(ram_num){
                case 0:{
                    //获取FPGA内部RAM参数
                    //read_fpga_ram(&MCU_RAM1[RAM_addr],RAM_addr, data_len);
                    //RAM0 参数帧率协议是4字节 其实是3字节
                    if(fpga_manage::MCU_REG_func[sel_fpga][FPGA_INIT_OK] != 0x03){
                        for(i=0;i<len;i++){
                            Rcv[2+i+FRAME_CMD] = 0x00;
                        }
                    }else{
                        fpga_manage::read_fpga_ram(&fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr],ram_addr, len,PARA_RAM,sel_fpga);
                        //Ouint16 value ;
                        //Ouint16 value1;
                        p_mcu_ram_back_eth_para = fpga_manage::p_fpga_manage->MCU_RAM_ETH_BACK_PARA_func[sel_fpga];
                        for(i=0;i<len;i++){
                            if(ram_addr+i==ETH_LCD_X || ram_addr+i==ETH_LCD_X + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH_LCD_X+ram_addr+i-ETH_LCD_X];

                            }else if(ram_addr+i==ETH_LCD_Y || ram_addr+i==ETH_LCD_Y + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BAKC_ETH_LCD_Y+ram_addr+i-ETH_LCD_Y];
                            }

                            if(ram_addr+i==ETH_LCD_W || ram_addr+i==ETH_LCD_W + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH_LCD_W+ram_addr+i-ETH_LCD_W];
                            }else if(ram_addr+i==ETH_LCD_H || ram_addr+i==ETH_LCD_H + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH_LCD_H+ram_addr+i-ETH_LCD_H];
                            }else if(ram_addr+i==ETH0_X || ram_addr+i==ETH0_X + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH0_X+ram_addr+i-ETH0_X];
                            }else if(ram_addr+i==ETH0_Y || ram_addr+i==ETH0_Y + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH0_Y+ram_addr+i-ETH0_Y];
                            }else if(ram_addr+i==ETH1_X || ram_addr+i==ETH1_X + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH1_X+ram_addr+i-ETH1_X];
                            }else if(ram_addr+i==ETH1_Y || ram_addr+i==ETH1_Y + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH1_Y+ram_addr+i-ETH1_Y];
                            }else if(ram_addr+i==ETH2_X || ram_addr+i==ETH2_X + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH2_X+ram_addr+i-ETH2_X];
                            }else if(ram_addr+i==ETH2_Y || ram_addr+i==ETH2_Y + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH2_Y+ram_addr+i-ETH2_Y];
                            }else if(ram_addr+i==ETH3_X || ram_addr+i==ETH3_X + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH3_X+ram_addr+i-ETH3_X];
                            }else if(ram_addr+i==ETH3_Y || ram_addr+i==ETH3_Y + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH3_Y+ram_addr+i-ETH3_Y];
                            }else if(ram_addr+i==ETH4_X || ram_addr+i==ETH4_X + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH4_X+ram_addr+i-ETH4_X];
                            }else if(ram_addr+i==ETH4_Y || ram_addr+i==ETH4_Y + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH4_Y+ram_addr+i-ETH4_Y];
                            }else if(ram_addr+i==ETH5_X || ram_addr+i==ETH5_X + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH5_X+ram_addr+i-ETH5_X];
                            }else if(ram_addr+i==ETH5_Y || ram_addr+i==ETH5_Y + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH5_Y+ram_addr+i-ETH5_Y];
                            }else if(ram_addr+i==ETH6_X || ram_addr+i==ETH6_X + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH6_X+ram_addr+i-ETH6_X];
                            }else if(ram_addr+i==ETH6_Y || ram_addr+i==ETH6_Y + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH6_Y+ram_addr+i-ETH6_Y];
                            }else if(ram_addr+i==ETH7_X || ram_addr+i==ETH7_X + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH7_X+ram_addr+i-ETH7_X];
                            }else if(ram_addr+i==ETH7_Y || ram_addr+i==ETH7_Y + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH7_Y+ram_addr+i-ETH7_Y];
                            }else if(ram_addr+i==ETH8_X || ram_addr+i==ETH8_X + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH8_X+ram_addr+i-ETH8_X];
                            }else if(ram_addr+i==ETH8_Y || ram_addr+i==ETH8_Y + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH8_Y+ram_addr+i-ETH8_Y];
                            }else if(ram_addr+i==ETH9_X || ram_addr+i==ETH9_X + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH9_X+ram_addr+i-ETH9_X];
                            }else if(ram_addr+i==ETH9_Y || ram_addr+i==ETH9_Y + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH9_Y+ram_addr+i-ETH9_Y];
                            }else if(ram_addr+i==ETH10_X || ram_addr+i==ETH10_X + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH10_X+ram_addr+i-ETH10_X];
                            }else if(ram_addr+i==ETH10_Y || ram_addr+i==ETH10_Y + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH10_Y+ram_addr+i-ETH10_Y];
                            }else if(ram_addr+i==ETH11_X || ram_addr+i==ETH11_X + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH11_X+ram_addr+i-ETH11_X];
                            }else if(ram_addr+i==ETH11_Y || ram_addr+i==ETH11_Y + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH11_Y+ram_addr+i-ETH11_Y];
                            }
                            //#if (defined OVP_G32)||(defined OVP_G24)
                            else if(ram_addr+i==ETH12_X || ram_addr+i==ETH12_X + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH12_X+ram_addr+i-ETH12_X];
                            }else if(ram_addr+i==ETH12_Y || ram_addr+i==ETH12_Y + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH12_Y+ram_addr+i-ETH12_Y];
                            }else if(ram_addr+i==ETH13_X || ram_addr+i==ETH13_X + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH13_X+ram_addr+i-ETH13_X];
                            }else if(ram_addr+i==ETH13_Y || ram_addr+i==ETH13_Y + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH13_Y+ram_addr+i-ETH13_Y];
                            }else if(ram_addr+i==ETH14_X || ram_addr+i==ETH14_X + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH14_X+ram_addr+i-ETH14_X];
                            }else if(ram_addr+i==ETH14_Y || ram_addr+i==ETH14_Y + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH14_Y+ram_addr+i-ETH14_Y];
                            }else if(ram_addr+i==ETH15_X || ram_addr+i==ETH15_X + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH15_X+ram_addr+i-ETH15_X];
                            }else if(ram_addr+i==ETH15_Y || ram_addr+i==ETH15_Y + 1){
                                fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i] = p_mcu_ram_back_eth_para[MCU_BACK_ETH15_Y+ram_addr+i-ETH15_Y];
                            }
                            //#endif
                        }

                        for(i=0;i<len;i++){
                            Rcv[2+i+FRAME_CMD] = fpga_manage::p_fpga_manage->MCU_RAM_PARA_func[sel_fpga][ram_addr+i];
                        }
                    }

                    break;
                }
                case 1:{
                    switch(len_num){
                        case 1:
                        case 3:
                        case 5:
                        case 7:
                        case 9:
                        case 11:
                        case 13:
                        case 15:
                        if(fpga_manage::MCU_REG_func[sel_fpga][FPGA_INIT_OK] != 0x03){

                            for(i=0;i<len;i++){
                                Rcv[2+i+FRAME_CMD] = 0x00;
                            }
                        }else{
                            fpga_manage::read_fpga_ram(fpga_manage::MCU_RAM_RX_func[sel_fpga],ram_addr,len,RX_RAM_12+len_num -1,sel_fpga);
                            for(i=0;i<len;i++){
                                Rcv[2+i+FRAME_CMD] = fpga_manage::MCU_RAM_RX_func[sel_fpga][i];
                            }
                        }
                        break;

                        case 2:
                        case 4:
                        case 6:
                        case 8:
                        case 10:
                        case 12:
                        case 14:
                        case 16:
                        if(fpga_manage::MCU_REG_func[sel_fpga][FPGA_INIT_OK] != 0x03){
                            for(i=0;i<len;i++){
                                Rcv[2+i+FRAME_CMD] = 0x00;
                            }
                        }else{
                            fpga_manage::read_fpga_ram(fpga_manage::MCU_RAM_TX_func[sel_fpga],ram_addr,len,TX_RAM_12+len_num-2,sel_fpga);
                            for(i=0;i<len;i++){
                                Rcv[2+i+FRAME_CMD] = fpga_manage::MCU_RAM_TX_func[sel_fpga][i];
                            }
                        }
                        break;
                        default:
                        break;
                    }
                    break;
                }
                case 2://!<res
                switch(len_num){
                case 0:
                    if(fpga_manage::MCU_REG_func[sel_fpga][FPGA_INIT_OK] != 0x03){
                        for(i=0;i<len;i++){
                            Rcv[2+i+FRAME_CMD] = 0x00;
                        }
                    }else{
                        fpga_manage::read_fpga_ram(fpga_manage::MCU_RAM_DEFAULT,ram_addr,len,RECEIVED_RAM,sel_fpga);
                        for(i=0;i<len;i++){
                                Rcv[2+i+FRAME_CMD] = fpga_manage::MCU_RAM_DEFAULT[i];
                        }
                    }
                    break;
                case 1:
                case 2:
                case 3:
                case 4:
                case 5:
                case 6:
                case 7:
                case 8:
                case 9:
                case 10:
                case 11:
                case 12:
                case 13:
                case 14:
                case 15:
                case 16:
                    if(fpga_manage::MCU_REG_func[sel_fpga][FPGA_INIT_OK] != 0x03){
                        for(i=0;i<len;i++){
                            Rcv[2+i+FRAME_CMD] = 0x00;
                        }
                    }else{
                        fpga_manage::read_fpga_ram(fpga_manage::MCU_RAM_ZOOM,ram_addr,len,LCD0_RAM_H+len_num-1,sel_fpga);
                        for(i=0;i<len;i++){
                                Rcv[2+i+FRAME_CMD] = fpga_manage::MCU_RAM_ZOOM[i];
                        }
                    }
                    break;
                }
                break;
                case 5://!<export
                for(i=0;i<len;i++){
                    Rcv[2+i+FRAME_CMD] = fpga_manage::MCU_RAM_CMD[i];
                }
                break;
                case 4:
                if(fpga_manage::MCU_REG_func[sel_fpga][FPGA_INIT_OK] != 0x03){
                    for(i=0;i<len;i++){
                        Rcv[2+i+FRAME_CMD] = 0x00;
                    }
                }else{
                    fpga_manage::read_fpga_ram(fpga_manage::MCU_RAM_TX_func[sel_fpga],ram_addr,len,CRC_RAM,sel_fpga);
                    for(i=0;i<len;i++){
                          Rcv[2+i+FRAME_CMD] = fpga_manage::MCU_RAM_TX_func[sel_fpga][i];
                    }
                }
                break;
                case 6://!<MCU just about
                FPGA_Ex_ram_update();
                Time_to_RAM();//!<时间不是实时记录到RAM区的，所以读取时记录
                for(i=0;i<len;i++){
                    Rcv[2+i+FRAME_CMD] = fpga_manage::MCU_RAM_EXTEND[start_addr+i];
                }
                break;

                default:
                break;
            }

        }else{

            Rcv[1+FRAME_CMD] = CMD_NACK_EXECUTION;
            len = 1;
        }
    }



    return (len + 1);
}

void message_deal::Time_to_RAM(void)
{
//     vector<string> time_list;
//     uint16 year_h,year_l;

//     QDateTime currentDateTime = QDateTime::currentDateTime();
//     QString time = currentDateTime.toString("yyyy/MM/dd/hh/mm/ss/ddd");

// //    BX_printf("\n\n%s\n\n",time.toStdString().data());

//     time_list = time.split('/');

//     year_h = (time_list.at(0).toUInt())/100;
//     year_l = (time_list.at(0).toUInt())%100;
//     fpga_manage::MCU_RAM_EXTEND[0x10] = HEC_to_BCD(year_l);
//     fpga_manage::MCU_RAM_EXTEND[0x11] = HEC_to_BCD(year_h);//year
//     fpga_manage::MCU_RAM_EXTEND[0x12] = HEC_to_BCD(time_list.at(1).toUInt());//month
//     fpga_manage::MCU_RAM_EXTEND[0x13] = HEC_to_BCD(time_list.at(2).toUInt());//date
//     fpga_manage::MCU_RAM_EXTEND[0x14] = HEC_to_BCD(time_list.at(3).toUInt());//hour
//     fpga_manage::MCU_RAM_EXTEND[0x15] = HEC_to_BCD(time_list.at(4).toUInt());//minute
//     fpga_manage::MCU_RAM_EXTEND[0x16] = HEC_to_BCD(time_list.at(5).toUInt());//second
}

void message_deal::FPGA_Ex_ram_update(void)
{
    fpga_manage::MCU_RAM_EXTEND[0x1C] = fpga_manage::MCU_REG_func[FPGA_MASTER_VBYONE1][0x40];
    fpga_manage::MCU_RAM_EXTEND[0x31] = 0x9f;
}


Ouint32 message_deal::param_save(Ouint8 *Rcv)
{
    Ouint8 valid = 0;
    Ouint8 flashName = FPGA_FLASH_VBYONE1;
    Ouint8 sel_fpga = FPGA_MASTER_VBYONE1;




    if((Rcv[FRAME_NETPORT]) >=1 && (Rcv[FRAME_NETPORT] <=2)){
        sel_fpga = Rcv[FRAME_NETPORT] - 1 + FPGA_MASTER_VBYONE1;
        flashName = Rcv[FRAME_NETPORT] - 1 + FPGA_FLASH_VBYONE1;
        valid=0;
    }else{
        sel_fpga = FPGA_MASTER_VBYONE1;
        valid = 1;
        flashName = FPGA_FLASH_VBYONE1;
    }



//    equ_type = 0xAA;

    if(valid==1){
        sel_fpga = FPGA_MASTER_VBYONE1;
        flashName = FPGA_FLASH_VBYONE1;

        //ExFlash_Erase_Format(FPGA_MASTER_FLASH,RAM_PARA_START_SEC,ERASE_4K,1);
        fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_ERASE(flashName,g_Global->RAM_PARA_START_SEC,ERASE_4K,1);

        Ouint8 *p_MCU_RAM_PARA_func = new Ouint8[FPGA_RAM_MAX_LEN+4] ;
        for(int i=0;i<FPGA_RAM_MAX_LEN ;i++){
            p_MCU_RAM_PARA_func[4+i] = fpga_manage:: MCU_RAM_PARA_func[sel_fpga][i];//just for G32 DRV
        }

        //ExFlash_WR(FPGA_MASTER_FLASH,RAM_PARA_BASE_ADD+1,MCU_RAM_PARA_func[FPGA_MASTER_NEAR_VBYEON],RAM_MAX_LEN);
        fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_WRITE(flashName,g_Global->RAM_PARA_BASE_ADD+1,p_MCU_RAM_PARA_func,RAM_MAX_LEN) ;

        for(int i=0;i<1 ;i++){
            p_MCU_RAM_PARA_func[4+i] = 0xaa;//just for G32 DRV
        }
        //ExFlash_WR(FPGA_MASTER_FLASH,RAM_PARA_BASE_ADD,&equ_type,1);
        fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_WRITE(flashName,g_Global->RAM_PARA_BASE_ADD,p_MCU_RAM_PARA_func,1) ;

        //ExFlash_RD(FPGA_MASTER_FLASH,RAM_PARA_BASE_ADD+1,RAM_MAX_LEN,MCU_RAM_PARA_func[FPGA_MASTER_NEAR_VBYEON]);
        fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_READ(flashName,g_Global->RAM_PARA_BASE_ADD+1,RAM_MAX_LEN,fpga_manage:: MCU_RAM_PARA_func[sel_fpga]);

        fpga_manage::p_fpga_manage->G32_back_mcu_set_net_para(sel_fpga);
        #if (defined OUTPUT_BOARD_2)
        sel_fpga = FPGA_MASTER_VBYONE2;
        flashName = FPGA_FLASH_VBYONE2;
        //ExFlash_Erase_Format(FPGA_BASE_FLASH,RAM_PARA_START_SEC,ERASE_4K,1);
        fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_ERASE(flashName,RAM_PARA_START_SEC,ERASE_4K,1);

        for(int i=0;i<FPGA_RAM_MAX_LEN ;i++){
            p_MCU_RAM_PARA_func[4+i] = fpga_manage:: MCU_RAM_PARA_func[sel_fpga][i];//just for G32 DRV
        }

        //ExFlash_WR(FPGA_BASE_FLASH,RAM_PARA_BASE_ADD+1,MCU_RAM_PARA_func[FPGA_SLAVER_NEAR_OUTMINTOR],RAM_MAX_LEN);
        fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_WRITE(flashName,RAM_PARA_BASE_ADD+1,p_MCU_RAM_PARA_func,RAM_MAX_LEN) ;

        for(int i=0;i<1 ;i++){
            p_MCU_RAM_PARA_func[4+i] = 0xaa;//just for G32 DRV
        }
        //ExFlash_WR(FPGA_BASE_FLASH,RAM_PARA_BASE_ADD,&equ_type,1);
        fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_WRITE(flashName,RAM_PARA_BASE_ADD,p_MCU_RAM_PARA_func,1) ;
        #endif

        delete p_MCU_RAM_PARA_func;
        p_MCU_RAM_PARA_func = NULL;

        #if (defined OUTPUT_BOARD_2)
        //ExFlash_RD(FPGA_BASE_FLASH,RAM_PARA_BASE_ADD+1,RAM_MAX_LEN,MCU_RAM_PARA_func[FPGA_SLAVER_NEAR_OUTMINTOR]);
        fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_READ(flashName,RAM_PARA_BASE_ADD+1,RAM_MAX_LEN,fpga_manage:: MCU_RAM_PARA_func[sel_fpga]);

        fpga_manage::p_fpga_manage->G32_back_mcu_set_net_para(sel_fpga);
        #endif
    }else{
        //ExFlash_Erase_Format(FPGA_BASE_FLASH+sel_fpga,RAM_PARA_START_SEC,ERASE_4K,1);
        fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_ERASE(flashName,g_Global->RAM_PARA_START_SEC,ERASE_4K,1);

        Ouint8 *p_MCU_RAM_PARA_func = new Ouint8[FPGA_RAM_MAX_LEN+4] ;
        for(int i=0;i<FPGA_RAM_MAX_LEN ;i++){
            p_MCU_RAM_PARA_func[4+i] = fpga_manage:: MCU_RAM_PARA_func[sel_fpga][i];//just for G32 DRV
        }
        //ExFlash_WR(FPGA_BASE_FLASH+sel_fpga,RAM_PARA_BASE_ADD+1,MCU_RAM_PARA_func[sel_fpga],RAM_MAX_LEN);
        fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_WRITE(flashName,g_Global->RAM_PARA_BASE_ADD+1,p_MCU_RAM_PARA_func,RAM_MAX_LEN) ;
        for(int i=0;i<1 ;i++){
            p_MCU_RAM_PARA_func[4+i] = 0xaa;//just for G32 DRV
        }
        //ExFlash_WR(FPGA_BASE_FLASH+sel_fpga,RAM_PARA_BASE_ADD,&equ_type,1);
        fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_WRITE(flashName,g_Global->RAM_PARA_BASE_ADD,p_MCU_RAM_PARA_func,1) ;
        delete p_MCU_RAM_PARA_func;
        p_MCU_RAM_PARA_func = NULL;
        //ExFlash_RD(FPGA_BASE_FLASH+sel_fpga,RAM_PARA_BASE_ADD+1,RAM_MAX_LEN,MCU_RAM_PARA_func[sel_fpga]);
        fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_READ(flashName,g_Global->RAM_PARA_BASE_ADD+1,RAM_MAX_LEN,fpga_manage:: MCU_RAM_PARA_func[sel_fpga]);

        fpga_manage::p_fpga_manage->G32_back_mcu_set_net_para(sel_fpga);
    }

    Rcv[1+FRAME_CMD] = 0x00 ;

    return 1;
}

/*
 *
 * @param
 * @return
 */
Ouint32 message_deal::get_card_version(Ouint8 *Rcv)
{
    Ouint16 src_addr =MCU_DEFAULT_ADDR;
    Ouint8 sel_fpga = FPGA_MASTER_VBYONE1;
    Ouint32 ret;

    src_addr = Rcv[FRAME_DST_ADDR_L] | Rcv[FRAME_DST_ADDR_H] << 8 ;

    if(src_addr == MCU_DEFAULT_ADDR || src_addr == MCU_DEFAULT_ADDR1){


    }else{
        //read fpga ver

        if(Rcv[FRAME_CONTROL_CLASS]==CONTROL_CLASS_TXC){
            if((Rcv[FRAME_NETPORT]>=1)&&(Rcv[FRAME_NETPORT]<=2)){
                sel_fpga = Rcv[FRAME_NETPORT]-1;
            }
        }


        Rcv[FRAME_CMD + 1] = 0x00;
        Rcv[FRAME_CMD + 2] = fpga_manage::MCU_REG_func[sel_fpga][FPGA_JUMP_REG] ;//0x00;
        Rcv[FRAME_CMD + 3] = CONTROL_CLASS_FPGA;
        Rcv[FRAME_CMD + 4] = g_Global->OVP_CONTROL_FPGA1 & 0x0FF;
        Rcv[FRAME_CMD + 5] = (g_Global->OVP_CONTROL_FPGA1 >> 8) & 0x0FF;
        Rcv[FRAME_CMD + 6] = 11;//BCD_to_HEC(fpga_manage::MCU_REG_func[sel_fpga][FPGA_HARD_PCB_VERSION]);//
        Rcv[FRAME_CMD + 7] = fpga_manage::MCU_REG_func[sel_fpga][FPGA_BYTE0_REG];//ver fun
        Rcv[FRAME_CMD + 8] = fpga_manage::MCU_REG_func[sel_fpga][FPGA_BYTE1_REG];//ver date
        Rcv[FRAME_CMD + 9] = fpga_manage::MCU_REG_func[sel_fpga][FPGA_BYTE2_REG];//ver month
        Rcv[FRAME_CMD + 10] = fpga_manage::MCU_REG_func[sel_fpga][FPGA_BYTE3_REG];//ver year
        Rcv[FRAME_CMD + 11] = 0x00;
        Rcv[FRAME_CMD + 12] = 0x00;
        Rcv[FRAME_CMD + 13] = fpga_manage::p_fpga_manage->Timeout_flag;


    }

    ret = G_timeTicks /20 ;

    Rcv[FRAME_CMD + 14] =  (ret >> 0) & 0x0FF;;
    Rcv[FRAME_CMD + 15] =  (ret >> 8) & 0x0FF;;
    Rcv[FRAME_CMD + 16] =  (ret >> 16) & 0x0FF;;
    Rcv[FRAME_CMD + 17] =  (ret >> 24) & 0x0FF;;

    return 17;
}

/*
 *
 * @param
 * @return
 */
Ouint32 message_deal::get_card_uid(Ouint8 *Rcv)
{
    Ouint16 src_addr =MCU_DEFAULT_ADDR;
    /*Ouint8 sel_fpga = FPGA_MASTER_VBYONE1;*/
//    Ouint32 ret;

    src_addr = Rcv[FRAME_DST_ADDR_L] | Rcv[FRAME_DST_ADDR_H] << 8 ;

    if(src_addr == MCU_DEFAULT_ADDR || src_addr == MCU_DEFAULT_ADDR1){
        Rcv[FRAME_CMD + 1] = CMD_NACK_EXECUTION;

        return 1;

    }else{
//      fpga_flash_access();
        Rcv[FRAME_CMD + 1] = CMD_ACK_NOERR;

        if(fpga_manage::p_fpga_manage != NULL){
            fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_SSTF016B_RD_UID(FPGA_FLASH_VBYONE1,&Rcv[FRAME_CMD + 2]);

            return 9;
        }
        //不回复
        else{

            return 0;
        }
    }


}

Ouint32 message_deal::start_update(Ouint8 *Rcv,Ouint32 len)
{
    Ouint8 fpga_flag = 0;
    Ouint8 valid = 0;
    Ouint8 sel_fpga = FPGA_FLASH_VBYONE1;
    Ouint8 crc_buf[256];
    Ouint16 src_addr =MCU_DEFAULT_ADDR;

    src_addr = Rcv[FRAME_DST_ADDR_L] | Rcv[FRAME_DST_ADDR_H] << 8 ;

    if(src_addr == MCU_DEFAULT_ADDR || src_addr == MCU_DEFAULT_ADDR1){

        Rcv[1+FRAME_CMD] = CMD_ACK_NOERR;
        return 1 ;
    }

    if(len == 10){
        fpga_flag=0x02;
    }else if(len == 11){
        fpga_flag = Rcv[FRAME_DST_ADDR_H+FRAME_CMD] & 0x02;
    }else{
        Rcv[1+FRAME_CMD] = CMD_NACK_EXECUTION;
    }

    if((Rcv[FRAME_NETPORT]) >=1 && (Rcv[FRAME_NETPORT] <=2)){
        sel_fpga = Rcv[FRAME_NETPORT] - 1;
        valid = 0;
    }else{
        valid = 1;
    }

    if(fpga_flag == 0x02){

        {
            fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_READ(FPGA_FLASH_VBYONE1,g_Global->PARAM1_SEC_ADDR+1,256,crc_buf) ;
            fpga_manage::p_fpga_manage->write_fpga_ram(crc_buf,0,256,10,FPGA_MASTER_VBYONE1);
            fpga_manage::p_fpga_manage->write_to_register(FPGA_CLEAR_REG,0x40,0x40,FPGA_MASTER_VBYONE1);
            //fpga_manage::MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_INIT_OK] = 0;
            //g_change.sys_fpga_delay_time[FPGA_MASTER_VBYONE1] = G_timeTicks;

            fpga_manage::p_fpga_manage->fpga1_rst_flag = true;
            fpga_manage::p_fpga_manage->fpga1_rst_ticks = G_timeTicks;
            fpga_manage::p_fpga_manage->fpga_init_rst_times[FPGA_MASTER_VBYONE1]=0x00;
//            system("echo 0 >/sys/class/gpio/gpio17/value");

            // *(unsigned short *)(fpga_manage::p_fpga_manage->to_fpga1_reset) = GPIO17_CONTENT_L ;
            fpga_manage::p_fpga_manage->setGpioHigLow(3, 10, 0) ;
        }

        Rcv[1+FRAME_CMD] = CMD_ACK_NOERR;

    }

    BX_printf("\n update ok! sel_fpga : %d valid : %d,len = %#x\n",sel_fpga, valid, len) ;
    //g_mainwindow->update_over();

    return 1;
}


/*
 *
 * @param
 * @return
 */
Ouint32 message_deal::write_rtc_time(Ouint8 *Rcv)
{
// //    uint16 src_addr = MCU_DEFAULT_ADDR;

// #if 0

//     src_addr = Rcv[FRAME_DST_ADDR_L] | Rcv[FRAME_DST_ADDR_H] << 8 ;


//     if(src_addr == MCU_DEFAULT_ADDR || src_addr == MCU_DEFAULT_ADDR1){

//         QDateTime dateTime = QDateTime::currentDateTime();
//         //dateTime = dateTime.addSecs(timeZone.remove("GMT").toInt()*60*60);



//         QString dateExp, timeExp, tmpExp, cmdExp;
//         dateExp = QString("%1-%2-%3").arg(dateTime.date().year(),0,10).arg(dateTime.date().month(),0,10).arg(dateTime.date().day(),0,10);
//         timeExp = QString("%1:%2:%3").arg(dateTime.time().hour(),0,10).arg(dateTime.time().minute(),0,10).arg(dateTime.time().second(),0,10);


//         BX_printf("\n onbon time = %s  %s\n",dateExp.toStdString().data() ,timeExp.toStdString().data() ) ;


//     }else{


//     }
// #else
//   #if 1
//         QString dateExp, timeExp, tmpExp, cmdExp;
//         int year,month,day,hour,minute,second;

//         year = BCD_to_HEC(Rcv[1+FRAME_CMD]) + BCD_to_HEC(Rcv[2+FRAME_CMD]) * 100;
//         month = BCD_to_HEC(Rcv[3+FRAME_CMD]);
//         day = BCD_to_HEC(Rcv[4+FRAME_CMD]);
//         hour = BCD_to_HEC(Rcv[5+FRAME_CMD]);
//         minute = BCD_to_HEC(Rcv[6+FRAME_CMD]);
//         second = BCD_to_HEC(Rcv[7+FRAME_CMD]);

// //        BX_printf("\n\n  year:%d month:%d day:%d hour:%d minute:%d second:%d\n ",year,month,day,hour,minute,second) ;

//         dateExp = QString("%1-%2-%3").arg(year,0,10).arg(month,0,10).arg(day,0,10);
//         timeExp = QString("%1:%2:%3").arg(hour,0,10).arg(minute,0,10).arg(second,0,10);

//         tmpExp = dateExp + QString(" ") + timeExp; //不能加week date命令标准格式为date “2013-1-1 12:14:32”
//         cmdExp = QString("date \"") + tmpExp + QString("\";hwclock -wu"); //设置系统时间并同步RTC时间

//         Utils::system_mutex(cmdExp,NULL);

//   #else
// //    c331_manage:: c331_print();


//     onbonsource::p_onbon_source->set_custom_edid = 1;



//   #endif

// #endif

//     Rcv[1+FRAME_CMD] = 0x00 ;


    return 1;
}



/*
 *
 * @param
 * @return
 */
Ouint32 message_deal::write_file_start(Ouint8 *Rcv)
{


    return 3;
}


/*
 *
 * @param
 * @return
 */
Ouint32 message_deal::write_defined_file_start(Ouint8 *Rcv)
{


    return 3;
}


/*
 *
 * @param
 * @return
 */
Ouint32 message_deal::write_file_block(Ouint8 *Rcv)
{


    return 2;
}


/*
 *
 * @param
 * @return
 */
Ouint32 message_deal::write_file_end(Ouint8 *Rcv)
{

    return 3;
}

/*
 *
 * @param
 * @return
 */
Ouint32 message_deal::read_file_start(Ouint8 *Rcv)
{

    return 7;
}



/*
 *
 * @param
 * @return
 */
Ouint32 message_deal::read_defined_file_start(Ouint8 *Rcv)
{

    return 7;
}


/*
 *
 * @param
 * @return
 */
Ouint32 message_deal::read_file_block(Ouint8 *Rcv)
{

    return (2);
}



/*
 *
 * @param
 * @return
 */
Ouint32 message_deal::read_file_end(Ouint8 *Rcv)
{


    return (2+16);
}



/*
 *
 * @param
 * @return
 */
Ouint32 message_deal::read_dir_file_para(Ouint8 *Rcv)
{
    return (2);
}

/*
 *
 * @param
 * @return
 */
Ouint32 message_deal::delete_file_name(Ouint8 *Rcv)
{

    Rcv[1+FRAME_CMD] = 0x00;
    Rcv[2+FRAME_CMD] = CMD_DELETE_FILE;


    return (2);
}

/*
 *
 * @param
 * @return
 */
Ouint32 message_deal::write_file_group(Ouint8 *Rcv)
{
    Ouint8 cmd = Rcv[1+FRAME_CMD];
    Ouint32 len = 0;


    switch (cmd) {
    case CMD_WRITE_FILE_START:
        len = write_file_start(Rcv);
        break;
    case CMD_WRITE_FILE_BLOCK:
        len = write_file_block(Rcv);
        break;
    case CMD_WRITE_FILE_END:
        len = write_file_end(Rcv);
        break;
    case CMD_READ_FILE_START:
        len = read_file_start(Rcv);
        break;
    case CMD_READ_FILE_BLOCK:
        len = read_file_block(Rcv);
        break;
    case CMD_READ_FILE_END:
        len = read_file_end(Rcv);
        break;
    case CMD_WRITE_DEFINED_FILE_START:
        len = write_defined_file_start(Rcv);
        break;
    case CMD_READ_DEFINED_FILE_START:
        len = read_defined_file_start(Rcv);
        break;
    case CMD_READ_DIR_FILE_PARA:
        len = read_dir_file_para(Rcv);
        break;
    case CMD_DELETE_FILE:
        len = delete_file_name(Rcv);
        break;
    default:
        break;
    }





    return len;
}




/*
 *
 * @param
 * @return
 */
Ouint8 message_deal::is_super_password(Ouint8* password)
{

    return 0;
}

Ouint8 message_deal::set_new_project_time(Ouint8 type , TimeRealType* rev_time , Ouint8* password,Ouint8 comm_id)
{
    Ouint8 i;
    Ouint8 buf[102];

    //Ouint8  flash_uid[16] = {0};

    //fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_SSTF016B_RD_UID(FPGA_FLASH_VBYONE1,flash_uid);
    fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_READ(FPGA_FLASH_VBYONE1,g_Global->TIME_FLAG_ADD,102,fpga_manage::p_fpga_manage->timeout_buf);

    if(fpga_manage::p_fpga_manage->timeout_buf[0] == 0xAA){

        if(fpga_manage::p_fpga_manage->timeout_buf[84] != 0x01){
            for(i = 0; i < 16; i++){
              if((fpga_manage::p_fpga_manage->timeout_buf[58 + i] != 0xFF)){
                if(fpga_manage::p_fpga_manage->timeout_buf[58 + i] != password[i]){
                    if(is_super_password(password) != 0){
                          return CMD_NACK_PASS_ERROR;
                    }
                }
              }
            }
        }

    }else{
        return 2;
    }

    for(i=0; i<102; i++){
        buf[i] = fpga_manage::p_fpga_manage->timeout_buf[i];
    }

    switch(type){
    case 0://!<立即锁定
    case 1://!<延长试用

        if(fpga_manage::p_fpga_manage->timeout_buf[84] == 0x01){
          if(UART_4G == comm_id){
             return CMD_NACK_LOCK_ERROR;
          }
        }

        buf[0] = 0xAA;

        buf[42] = HEC_to_BCD(fpga_manage::p_fpga_manage->read_time.year % 100);
        buf[43] = HEC_to_BCD((fpga_manage::p_fpga_manage->read_time.year / 100) & 0xff);
        buf[44] = HEC_to_BCD(fpga_manage::p_fpga_manage->read_time.month);
        buf[45] = HEC_to_BCD(fpga_manage::p_fpga_manage->read_time.date);
        buf[46] = HEC_to_BCD(fpga_manage::p_fpga_manage->read_time.hour);
        buf[47] = HEC_to_BCD(fpga_manage::p_fpga_manage->read_time.minute);
        buf[48] = HEC_to_BCD(fpga_manage::p_fpga_manage->read_time.second);
        buf[49] = HEC_to_BCD(fpga_manage::p_fpga_manage->read_time.week);

        buf[50] = HEC_to_BCD(rev_time->year % 100);
        buf[51] = HEC_to_BCD((rev_time->year / 100) & 0xff);
        buf[52] = HEC_to_BCD(rev_time->month);
        buf[53] = HEC_to_BCD(rev_time->date);
        buf[54] = HEC_to_BCD(rev_time->hour);
        buf[55] = HEC_to_BCD(rev_time->minute);
        buf[56] = HEC_to_BCD(rev_time->second);
        buf[57] = HEC_to_BCD(rev_time->week);

        buf[74] = Utils::BCC(buf, 74);
        buf[84] = 0xff;

      break;
    case 2://!<立即转正
        /*for(i = 0; i < 75; i++){
          timeout_buf[i] = 0xFF;
        }*/
        if(fpga_manage::p_fpga_manage->timeout_buf[84] == 0x01){
          if(UART_4G == comm_id){
             return CMD_NACK_LOCK_ERROR;
          }
        }
        buf[75] = 0xAA;
        buf[84] = 0x01;
      break;
    /*case 3://!<定时转正(已取消)
        timeout_buf[75] = 0xAA;
        timeout_buf[84] = 0x02;

        timeout_buf[76] = HEC_to_BCD(rev_time->year  % 100);
        timeout_buf[77] = HEC_to_BCD((rev_time->year / 100) & 0xff);
        timeout_buf[78] = HEC_to_BCD(rev_time->month);
        timeout_buf[79] = HEC_to_BCD(rev_time->date);
        timeout_buf[80] = HEC_to_BCD(rev_time->hour);
        timeout_buf[81] = HEC_to_BCD(rev_time->minute);
        timeout_buf[82] = HEC_to_BCD(rev_time->second);
        timeout_buf[83] = HEC_to_BCD(rev_time->week);
      break;*/
    default:
      return 3;
    }


        buf[101] = 0xff;
        Ouint8 *p_MCU_RAM_PARA_func = new Ouint8[102+4] ;
        for(int i=0;i<102 ;i++){
            p_MCU_RAM_PARA_func[4+i] = buf[i];//just for G32 DRV
        }


        fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_ERASE(FPGA_FLASH_VBYONE1,g_Global->TIME_FLAG,ERASE_4K,1) ;
        fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_WRITE(FPGA_FLASH_VBYONE1,g_Global->TIME_FLAG_ADD,p_MCU_RAM_PARA_func,sizeof(fpga_manage::p_fpga_manage->timeout_buf)) ;

        delete p_MCU_RAM_PARA_func;
        p_MCU_RAM_PARA_func = NULL;

        BX_printf("\n  flash has wirten!! timeout_buf[0]=%#x\n ",fpga_manage::p_fpga_manage->timeout_buf[0]) ;
        //fpga_manage::p_fpga_manage->Timeout_flag |= 0x01;


        if(UART_4G == comm_id){
            Utils::_rcv_lockor_mutex.lock();

            if(type == 0){
                fpga_manage::p_fpga_manage->rcv_locksend_over = OVP_RCV_LOCK_AT_ONCE_LOCK;  //立即锁定
                fpga_manage::p_fpga_manage->rcv_unlocksend_over = OVP_RCV_LOCK_AT_ONCE_LOCK;//立即锁定
            }else if(type == 1){
                fpga_manage::p_fpga_manage->rcv_locksend_over = OVP_RCV_LOCK_DELAY_TRIAL;  //延长试用
                fpga_manage::p_fpga_manage->rcv_unlocksend_over = OVP_RCV_LOCK_DELAY_TRIAL;//延长试用
            }else if(type == 2){
                fpga_manage::p_fpga_manage->rcv_locksend_over = OVP_RCV_LOCK_IMMEDIATE_PROBATION;  //立即转正
                fpga_manage::p_fpga_manage->rcv_unlocksend_over = OVP_RCV_LOCK_IMMEDIATE_PROBATION;//立即转正
            }
            fpga_manage::p_fpga_manage->to_rcv_sure_status = 2;
            fpga_manage::p_fpga_manage->to_rcv_sure_cmd_num = 0;
            Utils::_rcv_lockor_mutex.unlock();
            //BX_printf("\n got the 4G ..... type = %s \n" , ((type==1)?" delay ":"lock at once")   ) ;
        }
        fpga_manage::p_fpga_manage->new_check_time = true;

        return 0;
}

Ouint16 message_deal::project_lock_probation(Ouint8 *Rcv_messag ,Ouint8 comm_id)
{
      Ouint8 i,flag;
      Ouint8 random_num[32];
      Ouint8 time_msg[8];
      Ouint8 password[16];
      Ouint8 uid[16];
      //Ouint8  flash_uid[16] = {0};
      TimeRealType rev_time;

      //fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_SSTF016B_RD_UID(FPGA_FLASH_VBYONE1,flash_uid);


      for(i = 0; i < 32; i++){
          random_num[i] = Rcv_messag[3+i+FRAME_CMD];
      }


      for(i = 0; i < 8; i++){
          time_msg[i] = Rcv_messag[35+i+FRAME_CMD] ^ random_num[i];
      }

      rev_time.year = BCD_to_HEC(time_msg[1]) * 100 + BCD_to_HEC(time_msg[0]);
      rev_time.month = BCD_to_HEC(time_msg[2]);
      rev_time.date = BCD_to_HEC(time_msg[3]);
      rev_time.hour = BCD_to_HEC(time_msg[4]);
      rev_time.minute = BCD_to_HEC(time_msg[5]);
      rev_time.second = BCD_to_HEC(time_msg[6]);
      rev_time.week = BCD_to_HEC(time_msg[7]);


      for(i = 0; i < 16; i++){
          password[i] = Rcv_messag[43+i+FRAME_CMD] ^ random_num[16+i];
      }

      for(i = 0; i < 16; i++){
          uid[i] = Rcv_messag[59+i+FRAME_CMD] ^ random_num[8+i];

          if(uid[i] != fpga_manage::p_fpga_manage->flash_uid[i]){
            Rcv_messag[1+FRAME_CMD] = CMD_NACK_UID_ERROR;
            Rcv_messag[2+FRAME_CMD] = CMD_PROJECT_PROBATION;
            return 3;
          }
      }


      if(Rcv_messag[2+FRAME_CMD] == 0x00){//!<立即锁定
          flag = set_new_project_time(0,&fpga_manage::p_fpga_manage->read_time,password,comm_id);
      }else if(Rcv_messag[2+FRAME_CMD] == 0x01){//!<延长试用
          flag = set_new_project_time(1,&rev_time,password,comm_id);
      }else{
          flag = CMD_NACK_COMMAND;
      }



      Rcv_messag[1+FRAME_CMD] = flag;
      Rcv_messag[2+FRAME_CMD] = CMD_PROJECT_PROBATION;
      return 3;
}

Ouint16 message_deal::project_lock_change(Ouint8 *Rcv_messag,Ouint8 comm_id)
{
      Ouint8 i,flag;
      Ouint8 random_num[32];
      Ouint8 time_msg[8];
      Ouint8 password[16];
      Ouint8 uid[16];
      //Ouint8  flash_uid[16] = {0};
      TimeRealType rev_time;

      //fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_SSTF016B_RD_UID(FPGA_FLASH_VBYONE1,flash_uid);


      for(i = 0; i < 32; i++){
          random_num[i] = Rcv_messag[3+i+FRAME_CMD];
      }


      for(i = 0; i < 8; i++){
          time_msg[i] = Rcv_messag[35+i+FRAME_CMD] ^ random_num[i];
      }

      rev_time.year = BCD_to_HEC(time_msg[1]) * 100 + BCD_to_HEC(time_msg[0]);
      rev_time.month = BCD_to_HEC(time_msg[2]);
      rev_time.date = BCD_to_HEC(time_msg[3]);
      rev_time.hour = BCD_to_HEC(time_msg[4]);
      rev_time.minute = BCD_to_HEC(time_msg[5]);
      rev_time.second = BCD_to_HEC(time_msg[6]);
      rev_time.week = BCD_to_HEC(time_msg[7]);


      for(i = 0; i < 16; i++){
          password[i] = Rcv_messag[43+i+FRAME_CMD] ^ random_num[16+i];
      }


      for(i = 0; i < 16; i++){
          uid[i] = Rcv_messag[59+i+FRAME_CMD] ^ random_num[8+i];

          if(uid[i] != fpga_manage::p_fpga_manage->flash_uid[i]){
            Rcv_messag[1+FRAME_CMD] = CMD_NACK_UID_ERROR;
            Rcv_messag[2+FRAME_CMD] = CMD_PROJECT_REGULAR;
            return 3;
          }
      }



      if(Rcv_messag[2+FRAME_CMD] == 0x00){//!<立即转正
          flag = set_new_project_time(2,&fpga_manage::p_fpga_manage->read_time,password,comm_id);
      }else if(Rcv_messag[2+FRAME_CMD] == 0x01){//!<定时转正(已取消)
          //flag = set_new_project_time(3,&rev_time,password);
          flag = CMD_NACK_COMMAND;
      }else{
          flag = CMD_NACK_COMMAND;
      }


      Rcv_messag[1+FRAME_CMD] = flag;
      Rcv_messag[2+FRAME_CMD] = CMD_PROJECT_REGULAR;
      return 3;
}

Ouint16 message_deal::project_lock_password(Ouint8 *Rcv_messag,Ouint8 comm_id)
{
      Ouint8 i,flag;
      Ouint8 random_num[32];
      Ouint8 old_pass[16];
      Ouint8 new_pass[16];
      Ouint8 uid[16];
      //Ouint8  flash_uid[16] = {0};
      Ouint8 buf[102];

      //fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_SSTF016B_RD_UID(FPGA_FLASH_VBYONE1,flash_uid);


      if(Rcv_messag[2+FRAME_CMD] != 0x01){//!<密码修改
          Rcv_messag[1+FRAME_CMD] = CMD_NACK_COMMAND;
          Rcv_messag[2+FRAME_CMD] = CMD_PROJECT_PASSWORD;
          return 3;
      }

      if(UART_4G == comm_id){

          fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_READ(FPGA_FLASH_VBYONE1,g_Global->TIME_FLAG_ADD,102,fpga_manage::p_fpga_manage->timeout_buf);

          if(fpga_manage::p_fpga_manage->timeout_buf[84] == 0x01){

              return CMD_NACK_LOCK_ERROR;
          }
       }




      for(i = 0; i < 32; i++){
          random_num[i] = Rcv_messag[3+i+FRAME_CMD];
      }

      for(i = 0; i < 16; i++){
          old_pass[i] = Rcv_messag[35+i+FRAME_CMD] ^ random_num[i];
      }

      for(i = 0; i < 16; i++){
          new_pass[i] = Rcv_messag[51+i+FRAME_CMD] ^ random_num[16+i];
      }
      //前8uid
      for(i = 0; i < 16; i++){
          uid[i] = Rcv_messag[67+i+FRAME_CMD] ^ random_num[8+i];

          if(uid[i] != fpga_manage::p_fpga_manage->flash_uid[i]){
            Rcv_messag[1+FRAME_CMD] = CMD_NACK_UID_ERROR;
            Rcv_messag[2+FRAME_CMD] = CMD_PROJECT_PASSWORD;
            return 3;
          }
      }


      /**************************************************/
      fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_READ(FPGA_FLASH_VBYONE1,g_Global->TIME_FLAG_ADD,102,fpga_manage::p_fpga_manage->timeout_buf);
      if(fpga_manage::p_fpga_manage->timeout_buf[0] == 0xAA){

          for(i = 0; i < 16; i++){
              if(fpga_manage::p_fpga_manage->timeout_buf[58 + i] != old_pass[i]){
                  if(is_super_password(old_pass) != 0){
                      Rcv_messag[1+FRAME_CMD] = CMD_NACK_PASS_ERROR;
                      Rcv_messag[2+FRAME_CMD] = CMD_PROJECT_PASSWORD;
                      return 3;
                  }
              }
          }
      }else{
          Rcv_messag[2+FRAME_CMD] = CMD_NACK_EXECUTION;
          return 3;
      }
      /**************************************************/

      for(i=0; i<102; i++){
          buf[i] = fpga_manage::p_fpga_manage->timeout_buf[i];
      }

      for(i = 0; i < 16; i++){
            buf[85 + i] = buf[58 + i];
      }
      for(i = 0; i < 16; i++){
            buf[58 + i] = new_pass[i];
      }

      buf[74] = Utils::BCC(buf, 74);
      buf[101] = 0xff;

      Ouint8 *p_MCU_RAM_PARA_func = new Ouint8[102+4] ;
      for(int i=0;i<102 ;i++){
          p_MCU_RAM_PARA_func[4+i] = buf[i];//just for G32 DRV
      }


      fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_ERASE(FPGA_FLASH_VBYONE1,g_Global->TIME_FLAG,ERASE_4K,1) ;
      fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_WRITE(FPGA_FLASH_VBYONE1,g_Global->TIME_FLAG_ADD,p_MCU_RAM_PARA_func,sizeof(fpga_manage::p_fpga_manage->timeout_buf)) ;

      delete p_MCU_RAM_PARA_func;
      p_MCU_RAM_PARA_func = NULL;


      Rcv_messag[1+FRAME_CMD] = CMD_ACK_NOERR;
      Rcv_messag[2+FRAME_CMD] = CMD_PROJECT_PASSWORD;



      if(UART_4G == comm_id){
         Utils::_rcv_lockor_mutex.lock();
         fpga_manage::p_fpga_manage->rcv_locksend_over = OVP_RCV_LOCK_CHANGE_PASSWORD;
         fpga_manage::p_fpga_manage->rcv_unlocksend_over = OVP_RCV_LOCK_CHANGE_PASSWORD;
         fpga_manage::p_fpga_manage->to_rcv_sure_status = 2;
         fpga_manage::p_fpga_manage->to_rcv_sure_cmd_num = 0;
         Utils::_rcv_lockor_mutex.unlock();
         //BX_printf("\n got the 4G .....project_lock_password\n"    ) ;
      }

      fpga_manage::p_fpga_manage->new_check_time = true; fpga_manage::p_fpga_manage->new_check_time = true;

      return 3;
}

Ouint16 message_deal::project_lock_set(Ouint8 *Rcv_messag,Ouint8 comm_id)
{
      Ouint8 i,flag;
      Ouint8 random_num[32];
      Ouint8 start_time[8];
      Ouint8 end_time[8];
      Ouint8 old_pass[16];
      Ouint8 uid[16];
      Ouint8 buf[102];
      //Ouint8  flash_uid[16] = {0};

      //fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_SSTF016B_RD_UID(FPGA_FLASH_VBYONE1,flash_uid);

       if(UART_4G == comm_id){

          fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_READ(FPGA_FLASH_VBYONE1,g_Global->TIME_FLAG_ADD,101,fpga_manage::p_fpga_manage->timeout_buf);

          if(fpga_manage::p_fpga_manage->timeout_buf[84] == 0x01){

              return CMD_NACK_LOCK_ERROR;
          }
        }




      for(i = 0; i < 32; i++){
          random_num[i] = Rcv_messag[3+i+FRAME_CMD];
      }

      for(i = 0; i < 8; i++){
          start_time[i] = Rcv_messag[35+i+FRAME_CMD] ^ random_num[i];
      }

      for(i = 0; i < 8; i++){
          end_time[i] = Rcv_messag[43+i+FRAME_CMD] ^ random_num[i];
      }


      for(i = 0; i < 16; i++){
          old_pass[i] = Rcv_messag[51+i+FRAME_CMD] ^ random_num[16+i];
      }


      for(i = 0; i < 16; i++){
          uid[i] = Rcv_messag[67+i+FRAME_CMD] ^ random_num[8+i];

          if(uid[i] != fpga_manage::p_fpga_manage->flash_uid[i]){
            Rcv_messag[1+FRAME_CMD] = CMD_NACK_UID_ERROR;
            Rcv_messag[2+FRAME_CMD] = CMD_PROJECT_SET;
            return 3;
          }
      }


      /**************************************************/
      fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_READ(FPGA_FLASH_VBYONE1,g_Global->TIME_FLAG_ADD,102,fpga_manage::p_fpga_manage->timeout_buf);
      if((fpga_manage::p_fpga_manage->timeout_buf[0] == 0xAA)&&((fpga_manage::p_fpga_manage->timeout_buf[84] != 0x01))){
          for(i = 0; i < 16; i++){
              if(fpga_manage::p_fpga_manage->timeout_buf[58 + i] != old_pass[i]){
                  if(is_super_password(old_pass) != 0){
                      Rcv_messag[1+FRAME_CMD] = CMD_NACK_PASS_ERROR;
                      Rcv_messag[2+FRAME_CMD] = CMD_PROJECT_SET;
                      return 3;
                  }
              }
          }

      }
      /**************************************************/

      for(i=0; i<102; i++){
          buf[i] = fpga_manage::p_fpga_manage->timeout_buf[i];
      }

      for(i = 0; i < 8; i++){
          buf[42+i] = start_time[i];
      }

      for(i = 0; i < 8; i++){
          buf[50+i] = end_time[i];
      }

      for(i = 0; i < 16; i++){
            buf[85 + i] = buf[58 + i];
      }
      for(i = 0; i < 16; i++){
            buf[58 + i] = old_pass[i];
      }

      buf[0] = 0xAA;
      buf[74] = Utils::BCC(buf, 74);
      buf[101] = 0xFF;

       for(i = 0; i < 10; i++){
            buf[75 + i] = 0xFF;
      }



      Ouint8 *p_MCU_RAM_PARA_func = new Ouint8[102+4] ;
      for(int i=0;i<102 ;i++){
          p_MCU_RAM_PARA_func[4+i] = buf[i];//just for G32 DRV
      }


      fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_ERASE(FPGA_FLASH_VBYONE1,g_Global->TIME_FLAG,ERASE_4K,1) ;
      fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_WRITE(FPGA_FLASH_VBYONE1,g_Global->TIME_FLAG_ADD,p_MCU_RAM_PARA_func,sizeof(fpga_manage::p_fpga_manage->timeout_buf)) ;

      delete p_MCU_RAM_PARA_func;
      p_MCU_RAM_PARA_func = NULL;


      //fpga_manage::p_fpga_manage->Timeout_flag |= 0x01;
      //fpga_manage::p_fpga_manage->new_check_time = true;

      Rcv_messag[1+FRAME_CMD] = CMD_ACK_NOERR;
      Rcv_messag[2+FRAME_CMD] = CMD_PROJECT_SET;

      if(UART_4G == comm_id){
          Utils::_rcv_lockor_mutex.lock();
          fpga_manage::p_fpga_manage->rcv_locksend_over = OVP_RCV_LOCK_ACT_ATONCE;
          fpga_manage::p_fpga_manage->rcv_unlocksend_over = OVP_RCV_LOCK_ACT_ATONCE;
          fpga_manage::p_fpga_manage->to_rcv_sure_status = 2;
          fpga_manage::p_fpga_manage->to_rcv_sure_cmd_num = 0;
          Utils::_rcv_lockor_mutex.unlock();
          //BX_printf("\n got the 4G .....project_lock_set\n"    ) ;
      }
      fpga_manage::p_fpga_manage->new_check_time = true;

      return 3;
}

Ouint16 message_deal::project_lock_get(Ouint8 *Rcv_messag,Ouint8 comm_id)
{
     Ouint8 i,flag;
     Ouint8 random_num[32];
     Ouint8 start_time[8];
     Ouint8 end_time[8];
     Ouint8 old_pass[16];
     Ouint8 uid[16];
     //Ouint8  flash_uid[16] = {0};

     //fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_SSTF016B_RD_UID(FPGA_FLASH_VBYONE1,flash_uid);

     Rcv_messag[1+FRAME_CMD] = 0x00;
     Rcv_messag[2+FRAME_CMD] = CMD_PROJECT_GET;

     for(i = 0; i < 32; i++){
       random_num[i] = rand()%256;
     }

     Rcv_messag[3+FRAME_CMD] = 0x00;

     for(i = 0; i < 32; i++){
       Rcv_messag[4 + i+FRAME_CMD] = random_num[i];
     }

     /**************************************************/
     fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_READ(FPGA_FLASH_VBYONE1,g_Global->TIME_FLAG_ADD,101,fpga_manage::p_fpga_manage->timeout_buf);

         if((fpga_manage::p_fpga_manage->timeout_buf[0] == 0xAA)&&((fpga_manage::p_fpga_manage->timeout_buf[84] != 0x01))){
             Rcv_messag[36+FRAME_CMD] = 1 ^ random_num[15];
         }else{
             Rcv_messag[36+FRAME_CMD] = 0 ^ random_num[15];
         }

          Rcv_messag[37+FRAME_CMD] = ((fpga_manage::p_fpga_manage->Timeout_flag & 0x02)>>1) ^ random_num[16];

         for(i = 0; i < 8; i++){
            Rcv_messag[38 + i+FRAME_CMD] = fpga_manage::p_fpga_manage->timeout_buf[42+i] ^ random_num[i];
         }

          for(i = 0; i < 8; i++){
            Rcv_messag[46 + i+FRAME_CMD] = fpga_manage::p_fpga_manage->timeout_buf[50+i] ^ random_num[i];
         }


         for(i = 0; i < 16; i++){

             Rcv_messag[54+i+FRAME_CMD] = fpga_manage::p_fpga_manage->flash_uid[i] ^ random_num[8+i];
         }

          return 70;

     //}
}

Ouint16 message_deal::project_lock_checkword(Ouint8 *Rcv_messag,Ouint8 comm_id)
{
      Ouint8 i,flag = 0;
      Ouint8 random_num[32];
      Ouint8 input_pass[16];


      for(i = 0; i < 32; i++){
          random_num[i] = Rcv_messag[3+i+FRAME_CMD];
      }

      for(i = 0; i < 16; i++){
          input_pass[i] = Rcv_messag[35+i+FRAME_CMD] ^ random_num[16+i];
      }



      /**************************************************/
      fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_READ(FPGA_FLASH_VBYONE1,g_Global->TIME_FLAG_ADD,101,fpga_manage::p_fpga_manage->timeout_buf);

      if((fpga_manage::p_fpga_manage->timeout_buf[0] != 0xAA)||((fpga_manage::p_fpga_manage->timeout_buf[84] == 0x01))){
          flag = 1;//无密码
      }else{


          for(i = 0; i < 16; i++){
              if(fpga_manage::p_fpga_manage->timeout_buf[58 + i] != input_pass[i]){
                  if(is_super_password(input_pass) != 0){
                      flag = 2;//密码不匹配
                      break;
                  }
              }
          }




      }


      Rcv_messag[1+FRAME_CMD] = 0x00;
      Rcv_messag[2+FRAME_CMD] = CMD_PROJECT_CHECKWORD;

      for(i = 0; i < 32; i++){
          random_num[i] = rand()%256;
      }

      for(i = 0; i < 32; i++){
          Rcv_messag[3 + i+FRAME_CMD] = random_num[i];
      }

      if(flag == 0){//密码匹配
          Rcv_messag[35+FRAME_CMD] = 0x01 ^ random_num[0];
      }else if(flag == 1){//无密码
          Rcv_messag[35+FRAME_CMD] = 0x00 ^ random_num[0];
      }else{//密码不匹配
          Rcv_messag[35+FRAME_CMD] = 0x02 ^ random_num[0];
      }

      return 36;

}


Ouint16 message_deal::project_engineering_lock(Ouint8 *Rcv_messag,Ouint8 comm_id)
{
      Ouint8 i;
      Ouint8 random_num[32];
      Ouint8 input_pass[16];
      Ouint8 uid[16];
      Ouint8 buf[102];


      for(i=0; i<102; i++){
          buf[i] = fpga_manage::p_fpga_manage->timeout_buf[i];
      }


      for(i = 0; i < 32; i++){
          random_num[i] = Rcv_messag[3+i+FRAME_CMD];
      }

      for(i = 0; i < 16; i++){
          input_pass[i] = Rcv_messag[35+i+FRAME_CMD] ^ random_num[16+i];
      }

      /**************************************************/
      /*fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_READ(FPGA_FLASH_VBYONE1,TIME_FLAG_ADD,101,fpga_manage::p_fpga_manage->timeout_buf);

      if((fpga_manage::p_fpga_manage->timeout_buf[0] != 0xAA)||((fpga_manage::p_fpga_manage->timeout_buf[84] == 0x01))){
          flag = 1;//无密码
      }else{


          for(i = 0; i < 16; i++){
              if(fpga_manage::p_fpga_manage->timeout_buf[58 + i] != input_pass[i]){
                  if(is_super_password(input_pass) != 0){
                      flag = 2;//密码不匹配
                      break;
                  }
              }
          }




      }*/
      if(UART_4G == comm_id){

          //fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_READ(FPGA_FLASH_VBYONE1,TIME_FLAG_ADD,101,fpga_manage::p_fpga_manage->timeout_buf);

          //if(fpga_manage::p_fpga_manage->timeout_buf[84] == 0x01){

          //    return CMD_NACK_LOCK_ERROR;
          //}
       }

      //前8uid
      for(i = 0; i < 16; i++){
          uid[i] = Rcv_messag[51+i+FRAME_CMD] ^ random_num[8+i];

          if(uid[i] != fpga_manage::p_fpga_manage->flash_uid[i]){
            Rcv_messag[1+FRAME_CMD] = CMD_NACK_UID_ERROR;
            Rcv_messag[2+FRAME_CMD] = CMD_ENGINEERING_LOCK;
            return 3;
          }
      }



      /**************************************************/
      /*fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_READ(FPGA_FLASH_VBYONE1,TIME_FLAG_ADD,101,fpga_manage::p_fpga_manage->timeout_buf);
      if(fpga_manage::p_fpga_manage->timeout_buf[0] == 0xAA){

          for(i = 0; i < 16; i++){
              if(fpga_manage::p_fpga_manage->timeout_buf[58 + i] != old_pass[i]){
                  if(is_super_password(old_pass) != 0){
                      Rcv_messag[1+FRAME_CMD] = CMD_NACK_PASS_ERROR;
                      Rcv_messag[2+FRAME_CMD] = CMD_PROJECT_PASSWORD;
                      return 3;
                  }
              }
          }
      }else{
          Rcv_messag[2+FRAME_CMD] = CMD_NACK_EXECUTION;
          return 3;
      }*/
      /**************************************************/

      buf[0] = 0xAA;

      buf[42] = HEC_to_BCD(fpga_manage::p_fpga_manage->read_time.year % 100);
      buf[43] = HEC_to_BCD((fpga_manage::p_fpga_manage->read_time.year / 100) & 0xff);
      buf[44] = HEC_to_BCD(fpga_manage::p_fpga_manage->read_time.month);
      buf[45] = HEC_to_BCD(fpga_manage::p_fpga_manage->read_time.date);
      buf[46] = HEC_to_BCD(fpga_manage::p_fpga_manage->read_time.hour);
      buf[47] = HEC_to_BCD(fpga_manage::p_fpga_manage->read_time.minute);
      buf[48] = HEC_to_BCD(fpga_manage::p_fpga_manage->read_time.second);
      buf[49] = HEC_to_BCD(fpga_manage::p_fpga_manage->read_time.week);

      buf[50] = HEC_to_BCD(fpga_manage::p_fpga_manage->read_time.year % 100);
      buf[51] = HEC_to_BCD((fpga_manage::p_fpga_manage->read_time.year / 100) & 0xff);
      buf[52] = HEC_to_BCD(fpga_manage::p_fpga_manage->read_time.month);
      buf[53] = HEC_to_BCD(fpga_manage::p_fpga_manage->read_time.date);
      buf[54] = HEC_to_BCD(fpga_manage::p_fpga_manage->read_time.hour);
      buf[55] = HEC_to_BCD(fpga_manage::p_fpga_manage->read_time.minute);
      buf[56] = HEC_to_BCD(fpga_manage::p_fpga_manage->read_time.second);
      buf[57] = HEC_to_BCD(fpga_manage::p_fpga_manage->read_time.week);

      buf[74] = Utils::BCC(buf, 74);

      for(i = 0; i < 16; i++){
            buf[85 + i] = buf[58 + i];
      }
      for(i = 0; i < 16; i++){
            buf[58 + i] = input_pass[i];
      }

      buf[75] = 0xAA;
      buf[84] = 0xFF;
      buf[101] = 0x01;

      buf[74] = Utils::BCC(buf, 74);

      Ouint8 *p_MCU_RAM_PARA_func = new Ouint8[102+4] ;
      for(int i=0;i<102 ;i++){
          p_MCU_RAM_PARA_func[4+i] = buf[i];//just for G32 DRV
      }


      fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_ERASE(FPGA_FLASH_VBYONE1,g_Global->TIME_FLAG,ERASE_4K,1) ;
      fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_WRITE(FPGA_FLASH_VBYONE1,g_Global->TIME_FLAG_ADD,p_MCU_RAM_PARA_func,sizeof(fpga_manage::p_fpga_manage->timeout_buf)) ;

      delete p_MCU_RAM_PARA_func;
      p_MCU_RAM_PARA_func = NULL;


      Rcv_messag[1+FRAME_CMD] = CMD_ACK_NOERR;
      Rcv_messag[2+FRAME_CMD] = CMD_ENGINEERING_LOCK;

      //fpga_manage::p_fpga_manage->Timeout_flag |= 0x01;


      //if(UART_4G == comm_id){
         Utils::_rcv_lockor_mutex.lock();
         fpga_manage::p_fpga_manage->rcv_locksend_over = OVP_RCV_LOCK_CHANGE_PASSWORD;
         fpga_manage::p_fpga_manage->rcv_unlocksend_over = OVP_RCV_LOCK_CHANGE_PASSWORD;
         fpga_manage::p_fpga_manage->to_rcv_sure_status = 2;
         fpga_manage::p_fpga_manage->to_rcv_sure_cmd_num = 0;
         Utils::_rcv_lockor_mutex.unlock();
         BX_printf("\n now 99  project_engineering_lock \n");
      //}

      BX_printf("\n now  project_engineering_lock \n");
      fpga_manage::p_fpga_manage->new_check_time = true;

      return 3;

}

Ouint16 message_deal::project_engineering_unlock(Ouint8 *Rcv_messag ,Ouint8 comm_id)
{
      Ouint8 i,flag;
      Ouint8 random_num[32];
      Ouint8 uid[16];
      Ouint8 buf[102];


      for(i=0; i<102; i++){
          buf[i] = fpga_manage::p_fpga_manage->timeout_buf[i];
      }

      for(i = 0; i < 32; i++){
          random_num[i] = Rcv_messag[3+i+FRAME_CMD];
      }



      for(i = 0; i < 16; i++){
          uid[i] = Rcv_messag[35+i+FRAME_CMD] ^ random_num[8+i];

          //if(uid[i] != fpga_manage::p_fpga_manage->flash_uid[i]){
          //  Rcv_messag[1+FRAME_CMD] = CMD_NACK_UID_ERROR;
          //  Rcv_messag[2+FRAME_CMD] = CMD_ENGINEERING_UNLOCK;
          //  return 3;
          //}
      }

      BX_printf("\n now in  project_engineering_unlock\n") ;


      if(fpga_manage::p_fpga_manage->timeout_buf[84] == 0x01){
        //if(UART_4G == comm_id){
        //   return CMD_NACK_LOCK_ERROR;
        //}
      }


      buf[75] = 0xAA;
      buf[84] = 0x01;
      buf[101] = 0x00;
      //fpga_manage::p_fpga_manage->timeout_buf[75] = 0xAA;
      //fpga_manage::p_fpga_manage->timeout_buf[84] = 0x01;
      //fpga_manage::p_fpga_manage->timeout_buf[101] = 0x00;


      Ouint8 *p_MCU_RAM_PARA_func = new Ouint8[102+4] ;
      for(int i=0;i<102 ;i++){
          p_MCU_RAM_PARA_func[4+i] = buf[i];//fpga_manage::p_fpga_manage->timeout_buf[i];//just for G32 DRV
      }


      fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_ERASE(FPGA_FLASH_VBYONE1,g_Global->TIME_FLAG,ERASE_4K,1) ;
      fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_WRITE(FPGA_FLASH_VBYONE1,g_Global->TIME_FLAG_ADD,p_MCU_RAM_PARA_func,sizeof(fpga_manage::p_fpga_manage->timeout_buf)) ;

      delete p_MCU_RAM_PARA_func;
      p_MCU_RAM_PARA_func = NULL;

      BX_printf("\n  flash has wirten!! timeout_buf[0]=%#x\n ",buf[0]) ;
      //fpga_manage::p_fpga_manage->Timeout_flag |= 0x01;


      //if(UART_4G == comm_id){
          Utils::_rcv_lockor_mutex.lock();

          fpga_manage::p_fpga_manage->rcv_locksend_over = OVP_RCV_LOCK_IMMEDIATE_PROBATION;  //立即转正
          fpga_manage::p_fpga_manage->rcv_unlocksend_over = OVP_RCV_LOCK_IMMEDIATE_PROBATION;//立即转正

          fpga_manage::p_fpga_manage->to_rcv_sure_status = 2;
          fpga_manage::p_fpga_manage->to_rcv_sure_cmd_num = 0;
          Utils::_rcv_lockor_mutex.unlock();
          BX_printf("\n start to project_engineering_unlock \n");

      //}
          fpga_manage::p_fpga_manage->new_check_time = true;

      Rcv_messag[1+FRAME_CMD] = flag;
      Rcv_messag[2+FRAME_CMD] = CMD_ENGINEERING_UNLOCK;
      return 3;
}


/*
 *
 * @param
 * @return
 */
Ouint32 message_deal::project_lock_group(Ouint8 *Rcv, Ouint8 comm_id)
{
    Ouint8 cmd = Rcv[1+FRAME_CMD];
    Ouint32 len = 0;

    switch (cmd){
                case CMD_PROJECT_PROBATION:{//!!<试用期变更
                        len = project_lock_probation(Rcv,comm_id);
                        break;
                }
                case CMD_PROJECT_REGULAR:{//!<试用期转正
                        len = project_lock_change(Rcv,comm_id);
                        break;
                }
                case CMD_PROJECT_PASSWORD:{//!<密码修改
                        len = project_lock_password(Rcv,comm_id);
                        break;
                }
                case CMD_PROJECT_SET:{//!<设置工程锁
                        len = project_lock_set(Rcv,comm_id);
                        break;
                }
                case CMD_PROJECT_GET:{//!<获取工程锁参数
                        len = project_lock_get(Rcv,comm_id);
                        break;
                }
                case CMD_PROJECT_CHECKWORD:{//!<密码校验
                        len = project_lock_checkword(Rcv,comm_id);
                        break;
                }
                case CMD_ENGINEERING_LOCK:{//!<工程锁锁定
                        len = project_engineering_lock(Rcv,comm_id);
                        break;
                }
                case CMD_ENGINEERING_UNLOCK:{//!<工程锁解锁
                        len = project_engineering_unlock(Rcv,comm_id);
                    break;
                }
        default:{
            //len = Send_ACK(Rcv_messag,CMD_NACK_COMMAND);
            break;
        }
    }
    return len;
}

/*
 *
 * @param
 * @return
 */
Ouint32 message_deal::write_register(Ouint8 *Rcv)
{
#if 1
    Ouint16 src_addr = MCU_DEFAULT_ADDR;
//    uint16 ret_len;
    Ouint8 temp;
    Ouint8 reg_addr;
    Ouint8 reg_mask;
    Ouint8 reg_data;
    Ouint8 ret=0;
    Ouint8 valid = 0;

    Ouint8 sel_fpag = FPGA_MASTER_VBYONE1;

    src_addr = Rcv[FRAME_DST_ADDR_L] | Rcv[FRAME_DST_ADDR_H] << 8 ;

    reg_addr = Rcv[1+FRAME_CMD];	//!<寄存器地址
    reg_mask = Rcv[2+FRAME_CMD];
    reg_data = Rcv[4+FRAME_CMD];
    if(reg_addr < REG_MAX_NUM){

        if(src_addr == MCU_DEFAULT_ADDR || src_addr == MCU_DEFAULT_ADDR1){
             //0C 0D寄存器不允许被写

        }else{
            //FPGA部分
             //FPGA部分
           if((Rcv[FRAME_NETPORT]>=1)&&(Rcv[FRAME_NETPORT]<=2 )){
                sel_fpag = Rcv[FRAME_NETPORT]-1;
                valid = 0;
           }else{
                valid = 1;
           }

            fpga_manage::p_fpga_manage->write_to_register(reg_addr,reg_mask,reg_data,sel_fpag);

            ret=0;

        }
        Rcv[1+FRAME_CMD] = ( (ret == 1) ?CMD_NACK_EXECUTION : CMD_ACK_NOERR) ;

    }else{
        Rcv[1+FRAME_CMD] = CMD_NACK_EXECUTION;
    }
    return 1;
#endif
}




/*
 *
 * @param
 * @return
 */
Ouint32 message_deal::read_register(Ouint8 *Rcv)
{
    Ouint16 ret_len;
    Ouint16 src_addr = MCU_DEFAULT_ADDR;
    Ouint8 reg_addr;
    Ouint8 sel_fpag = FPGA_MASTER_VBYONE1;

    reg_addr = Rcv[1+FRAME_CMD];
    src_addr = Rcv[FRAME_DST_ADDR_L] | Rcv[FRAME_DST_ADDR_H] << 8 ;
    if(reg_addr < REG_MAX_NUM){
        Rcv[1+FRAME_CMD] = CMD_ACK_NOERR;

        if(src_addr == MCU_DEFAULT_ADDR || src_addr == MCU_DEFAULT_ADDR1){
            switch(reg_addr){
            case 0x04:
            break;
            case 0x06://!<用户模式状态
            break;
            case 0x09://!<通讯标志



            Rcv[2+FRAME_CMD] = 0x00;
            break;
            //case REG_MCU_FLAG:
            //Rcv_messag[2] = g_ram_pc_para[reg_addr];
            //break;
            default:
            Rcv[2+FRAME_CMD] = 0x00;//g_ram_pc_para[reg_addr];
            break;
            }
        }else{
            if((Rcv[FRAME_NETPORT]>=1)&&(Rcv[FRAME_NETPORT]<=2 )){
                sel_fpag = Rcv[FRAME_NETPORT]-1;
            }

            fpga_manage::p_fpga_manage->read_from_register(reg_addr,sel_fpag);
            Rcv[2+FRAME_CMD] = fpga_manage::p_fpga_manage->MCU_REG_func[sel_fpag][reg_addr];
        }
        ret_len = 2;
    }else{
        Rcv[2+FRAME_CMD] = CMD_NACK_EXECUTION;
        ret_len = 2;
    }
    return ret_len;

}

/*
 *
 * @param
 * @return
 */
Ouint16 message_deal::cmd_erase_flash(Ouint8 *Rcv)
{
    Ouint16 src_addr = MCU_DEFAULT_ADDR;
    Ouint32	addr,tmp_addr,max_addr;
    Ouint32	erase_mode=ERASE_4K;
    Ouint16	ret_len = 1;
    Ouint16	start_block;
    Ouint16	offset=1;
    Ouint8	erase_type;
    Ouint8	erase_times;
    Ouint8	flashName=FPGA_FLASH_VBYONE1;
    Ouint8	flag;
    Ouint8	valid = 0;
    //int fd = fpga_manage::p_fpga_manage->fpga_vbyone1_flash_fd;

    src_addr = Rcv[FRAME_DST_ADDR_L] | Rcv[FRAME_DST_ADDR_H] << 8 ;
    addr = (Rcv[4+FRAME_CMD]<<24)|(Rcv[3+FRAME_CMD]<<16)|(Rcv[2+FRAME_CMD]<<8)|Rcv[1+FRAME_CMD];
    erase_type = Rcv[5+FRAME_CMD];
    erase_times = Rcv[6+FRAME_CMD];
    if(erase_times == 0)
        erase_times = 1;

    if(src_addr == MCU_DEFAULT_ADDR || src_addr == MCU_DEFAULT_ADDR1){
         tmp_addr = addr;
         tmp_addr = (tmp_addr>>24)&0xFF;
         addr = addr & 0x00FFFFFF;

    }else{
        if(Rcv[FRAME_CONTROL_CLASS]==CONTROL_CLASS_TXC){
            if((Rcv[FRAME_NETPORT]>=1)&&(Rcv[FRAME_NETPORT]<=2 )){
                 tmp_addr = Rcv[FRAME_NETPORT]+1;
                 valid=0;
            }else{
                tmp_addr=FPGA_FLASH_VBYONE1;//FPGA_MASTER_FLASH;
                valid=1;
            }

        }else{
             tmp_addr=FPGA_FLASH_VBYONE1;//FPGA_MASTER_FLASH;
        }
         addr = addr & 0x00FFFFFF;
        //start_block = addr/SEC_SIZE;

    }
     start_block = addr/g_Global->FLASH_SEC_SIZE;



     switch(tmp_addr){
         case 4:
         flashName = C331_FONT_FLASH;
         max_addr = g_Global->C331_FLASH_MAX_ADDR;
         break;
         case 2://是求靠近VBYONE的是 FPGA2
         flashName = FPGA_FLASH_VBYONE1;
         max_addr = g_Global->FPGA_FLASH_VBYONE1_MAX_ADDR;
         //fd = fpga_manage::p_fpga_manage->fpga_vbyone1_flash_fd ;
         break;
         case 3://靠近预监的是 FPGA1
         flashName = FPGA_FLASH_VBYONE2;
         max_addr = g_Global->FPGA_FLASH_VBYONE2_MAX_ADDR;
         // fd = fpga_manage::p_fpga_manage->fpga_vbyone2_flash_fd ;
         break;
         case SOURCE_CHIP_FLASH:
         flashName = SOURCE_CHIP_FLASH;
         max_addr = g_Global->SOURCE_CHIP_FLASH_MAX_ADDR;
         break;
         default:
         flashName = FPGA_FLASH_VBYONE1;
         max_addr = g_Global->FPGA_FLASH_VBYONE1_MAX_ADDR;
         //fd = fpga_manage::p_fpga_manage->fpga_vbyone1_flash_fd ;
         break;
     }


     if(addr%g_Global->FLASH_SEC_SIZE){//!<alignment by 4kb bits
         Rcv[1+FRAME_CMD] = CMD_NACK_EXECUTION;

         return ret_len;
     }
     flag = 0;
     switch(erase_type){
         case ERASE_TYPE_4K:
         offset = erase_times-1;
         erase_mode = ERASE_4K;
         break;
         case ERASE_TYPE_32K:
         offset = 8*erase_times-1;
         erase_mode = ERASE_32K;
         if(start_block%8)
             flag = 1;
         break;
         case ERASE_TYPE_64K:
         offset = 16*erase_times-1;
         erase_mode = ERASE_64K;
         if(start_block%16)
             flag = 1;
         break;
         default:
         flag = 1;
         break;
     }

     if(flag ==  1){
         Rcv[1+FRAME_CMD] = CMD_NACK_EXECUTION;

         return 1;
     }

    if(start_block+offset < max_addr/g_Global->FLASH_SEC_SIZE){


        if(tmp_addr == 4){

        }else if(tmp_addr == SOURCE_CHIP_FLASH){
            BX_printf("\n got the source chip earse  start_block=%#x erase_mode=%#x erase_times=%#x\n",start_block,erase_mode,erase_times) ;

        }
        else{

        fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_ERASE(flashName,start_block, erase_mode,erase_times) ;

        }





        Rcv[1+FRAME_CMD] = CMD_ACK_NOERR;
    }else{
         Rcv[1+FRAME_CMD] = CMD_NACK_EXECUTION;
    }

    return ret_len;
}


/*
 *
 * @param
 * @return
 */
Ouint16 message_deal::cmd_write_flash(Ouint8 *Rcv)
{
    Ouint16 src_addr = MCU_DEFAULT_ADDR;
    Ouint32	addr,tmp_addr,max_addr;
    Ouint16	ret_len = 1;
//    uint16	start_block;
//    uint16	offset;
    Ouint16 data_len;
    Ouint8 *data_p;
    Ouint8 flashName=FPGA_FLASH_VBYONE1;
    Ouint8 valid = 0;
    //int fd = fpga_manage::p_fpga_manage->fpga_vbyone1_flash_fd;

    src_addr = Rcv[FRAME_DST_ADDR_L] | Rcv[FRAME_DST_ADDR_H] << 8 ;
    addr = (Rcv[4+FRAME_CMD]<<24)|(Rcv[3+FRAME_CMD]<<16)|(Rcv[2+FRAME_CMD]<<8)|Rcv[1+FRAME_CMD];
    data_len = (Rcv[6+FRAME_CMD]<<8)|Rcv[5+FRAME_CMD];
    data_p = &Rcv[5+FRAME_CMD];//9+FRAME_CMD


    if(src_addr == MCU_DEFAULT_ADDR || src_addr == MCU_DEFAULT_ADDR1){
         tmp_addr = addr;
         tmp_addr = (tmp_addr>>24)&0xFF;
         addr = addr & 0x00FFFFFF;

    }else{
        if(Rcv[FRAME_CONTROL_CLASS]==CONTROL_CLASS_TXC){
            if((Rcv[FRAME_NETPORT]>=1)&&(Rcv[FRAME_NETPORT]<=2 )){
                 tmp_addr = Rcv[FRAME_NETPORT]+1;
                 valid=0;
            }else{
                tmp_addr=FPGA_FLASH_VBYONE1;//FPGA_MASTER_FLASH;
                valid=1;
            }

        }else{
             tmp_addr=FPGA_FLASH_VBYONE1;//FPGA_MASTER_FLASH;
        }
         addr = addr & 0x00FFFFFF;
        //start_block = addr/SEC_SIZE;

    }
//     start_block = addr/FLASH_SEC_SIZE;

//     BX_printf("\n erase temp_addr = %#x addr=%#x data_len=%#x \n",tmp_addr,addr,data_len) ;

     switch(tmp_addr){
         case 4:
         flashName = C331_FONT_FLASH;
         max_addr = g_Global->C331_FLASH_MAX_ADDR;
         break;
         case 2://vbyone1
         flashName = FPGA_FLASH_VBYONE1;
         max_addr = g_Global->FPGA_FLASH_VBYONE1_MAX_ADDR;
         //fd = fpga_manage::p_fpga_manage->fpga_vbyone1_flash_fd ;
         break;
         case 3://vbyone2
         flashName = FPGA_FLASH_VBYONE2;
         max_addr = g_Global->FPGA_FLASH_VBYONE2_MAX_ADDR;
         //fd = fpga_manage::p_fpga_manage->fpga_vbyone2_flash_fd ;
         break;
         case SOURCE_CHIP_FLASH:
         flashName = SOURCE_CHIP_FLASH;
         max_addr = g_Global->SOURCE_CHIP_FLASH_MAX_ADDR;
         break;
         default:
         flashName = FPGA_FLASH_VBYONE1;
         max_addr = g_Global->FPGA_FLASH_VBYONE1_MAX_ADDR;
         //fd = fpga_manage::p_fpga_manage->fpga_vbyone1_flash_fd ;
         break;
     }


      if((addr+data_len - 1) < max_addr){

          if(tmp_addr == 4){

          }else if(tmp_addr == SOURCE_CHIP_FLASH){
              BX_printf("\n got the source chip write falsh  addr=%#x data_len=%#x \n",addr,data_len) ;

          }
          else{

          fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_WRITE(flashName,addr, data_p,data_len) ;
          }

          Rcv[1+FRAME_CMD] = CMD_ACK_NOERR;
      }else{
         Rcv[1+FRAME_CMD] = CMD_NACK_EXECUTION;
      }

     return ret_len;
}


/*
 *
 * @param
 * @return
 */
Ouint16 message_deal::cmd_read_flash(Ouint8 *Rcv)
{
    Ouint16 src_addr = MCU_DEFAULT_ADDR;
    Ouint32 addr,tmp_addr,max_addr;
    Ouint16 data_len;
    Ouint16 ret_len = 1;
    Ouint8 flashName=FPGA_FLASH_VBYONE1;
    //int fd = fpga_manage::p_fpga_manage->fpga_vbyone1_flash_fd;
    addr = (Rcv[4+FRAME_CMD]<<24)|(Rcv[3+FRAME_CMD]<<16)|(Rcv[2+FRAME_CMD]<<8)|Rcv[1+FRAME_CMD];
    data_len = (Rcv[6+FRAME_CMD]<<8)|Rcv[5+FRAME_CMD];

    if(src_addr == MCU_DEFAULT_ADDR || src_addr == MCU_DEFAULT_ADDR1){
        tmp_addr = addr;
        tmp_addr = (tmp_addr>>24)&0xFF;

    }else{

        if(Rcv[FRAME_CONTROL_CLASS]==CONTROL_CLASS_TXC){
            if((Rcv[FRAME_NETPORT]>=1)&&(Rcv[FRAME_NETPORT]<=2 )){
                tmp_addr = Rcv[FRAME_NETPORT]+1;
           }else{
               tmp_addr=FPGA_FLASH_VBYONE1;
           }
       }else{
            tmp_addr=FPGA_FLASH_VBYONE1;
       }
       //addr = addr & 0x00FFFFFF;
    }
     addr = addr & 0x00FFFFFF;

    switch(tmp_addr){
        case 4:
        flashName = C331_FONT_FLASH;
        max_addr = g_Global->C331_FLASH_MAX_ADDR;
        break;
        case 2://vbyone1
        flashName = FPGA_FLASH_VBYONE1;
        max_addr = g_Global->FPGA_FLASH_VBYONE1_MAX_ADDR;//FLASH_2M_ADDR;4M
        //fd = fpga_manage::p_fpga_manage->fpga_vbyone1_flash_fd ;
        break;
        case 3://vbyone2
        flashName = FPGA_FLASH_VBYONE2;
        max_addr = g_Global->FPGA_FLASH_VBYONE2_MAX_ADDR;
        //fd = fpga_manage::p_fpga_manage->fpga_vbyone2_flash_fd ;
        break;
        case SOURCE_CHIP_FLASH:
        flashName = SOURCE_CHIP_FLASH;
        max_addr = g_Global->SOURCE_CHIP_FLASH_MAX_ADDR;
        break;
        default:
        flashName = FPGA_FLASH_VBYONE1;
        max_addr = g_Global->FPGA_FLASH_VBYONE1_MAX_ADDR;
        //fd = fpga_manage::p_fpga_manage->fpga_vbyone1_flash_fd ;
        break;
    }

    if((addr+data_len - 1) < max_addr){

        if(tmp_addr == 4){


        }else if(tmp_addr == SOURCE_CHIP_FLASH){
            BX_printf("\n got the source chip read falsh  addr=%#x data_len=%#x \n",addr,data_len) ;

        }else{


        fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_READ(flashName,addr, data_len,&Rcv[2+FRAME_CMD]) ;
        }
        Rcv[1+FRAME_CMD] = CMD_ACK_NOERR;
        ret_len = data_len+1;
    }else{
        Rcv[1+FRAME_CMD] = CMD_NACK_EXECUTION;
    }

    return ret_len;

}

/*
 *
 * @param
 * @return
 */
Ouint32 message_deal::message_group_deal(Ouint8 *Rcv ,Ouint32 le, Ouint8 comm_id)
{
    Ouint32 len = 0;

//    BX_printf("\n---\n---\n");
//    BX_printf("\n got the cmd = %02x ======le==%d\n ", Rcv[FRAME_CMD],le) ;

    switch (Rcv[FRAME_CMD]) {
    case CMD_RAM_WRITE:
        len = write_ram(Rcv);
        break;
    case CMD_RAM_READ:
        len = read_ram(Rcv);
        break;
    case CMD_PARAM_SAVE:
        len = param_save(Rcv);
        break;
    case CMD_GET_CARD_VERSION:
        len = get_card_version(Rcv);
        break;
    case CMD_GET_CARD_UID:
        len = get_card_uid(Rcv);
        break;
    case CMD_START_UPDATE:
        len = start_update(Rcv,le);
        break;
    case CMD_ADJUST_TIME:
        len = write_rtc_time(Rcv);
        break;
    case CMD_WRITE_FILE_GROUP:
        len = write_file_group(Rcv);
        break;
    case CMD_LOCK_TIME:
        len = project_lock_group(Rcv, comm_id);
        break;
    case CMD_4G_MODULE_GROUP:
        //len = p_message_deal_4g->message_deal_4G(Rcv);
        break;
    case CMD_REGISTER_WRITE:
        len = write_register(Rcv);
        break;
    case CMD_REGISTER_READ:
        len = read_register(Rcv);
        break;
    case CMD_FLASH_ERASE:
        len = cmd_erase_flash(Rcv);
        break;
    case CMD_FLASH_WRITE:
        len = cmd_write_flash(Rcv);
        break;
    case CMD_FLASH_READ:
        len = cmd_read_flash(Rcv);
        break;

    default:
        //BX_printf("other cmd : %02x ", Rcv[FRAME_CMD]) ;
        break;
    }

//    OvpRamPara::p_ovprampara_config->test_signal();

    return len;
}

/*
 * 数据反转义
 * @param
 * @return
 */
Ouint32 message_deal::data_transf_meaning(Ouint8 *sData, Ouint8 *cmdBuf,Ouint32 len,Ouint8 *frame_status)
{

    Oint32 i = 0;
    Ouint32 bufLen = 0;
   /* if(sData.len > PHY_DATA_LEN) {
        return 0;
    }*/

    rcv_state = PHY_R_INITIAL_STATE;
    *frame_status = 0;

    for(i = 0 ;i < len ;i++) {
        if(sData[i] == PHY_HEAD_VALUE){
            bufLen = 0;
            rcv_state = PHY_R_NORMAL_STATE;
            *frame_status = 0;
        }else if(rcv_state != PHY_R_INITIAL_STATE){
            switch (sData[i]) {
            case PHY_TRAIL_VALUE:
                rcv_state = PHY_R_INITIAL_STATE;
                i = len ; //quit
                *frame_status = 1;
                break;

            case PHY_TRANSFER_start_VALUE:
                rcv_state = PHY_R_TRANSFER_STATE1;
                break;

            case PHY_TRANSFER_end_VALUE:
                rcv_state = PHY_R_TRANSFER_STATE2;
                break;

            case PHY_TRANSFER_FLAG0:
                if(rcv_state == PHY_R_TRANSFER_STATE1){
                    cmdBuf[bufLen++] = PHY_HEAD_VALUE;
                }else if(rcv_state == PHY_R_TRANSFER_STATE2){
                    cmdBuf[bufLen++] = PHY_TRAIL_VALUE;
                }else{
                    cmdBuf[bufLen++] = sData[i];
                }
                rcv_state = PHY_R_NORMAL_STATE;
                break;

            case PHY_TRANSFER_FLAG1:
                if(rcv_state == PHY_R_TRANSFER_STATE1){
                    cmdBuf[bufLen++] = PHY_TRANSFER_start_VALUE;
                }else if(rcv_state == PHY_R_TRANSFER_STATE2){
                    cmdBuf[bufLen++] = PHY_TRANSFER_end_VALUE;
                }else{
                    cmdBuf[bufLen++] = sData[i];
                }
                rcv_state = PHY_R_NORMAL_STATE;
                break;

            default:
                if(rcv_state == !PHY_R_NORMAL_STATE) {
                    bufLen = 0;
                    rcv_state = PHY_R_INITIAL_STATE;
                    *frame_status = 0;
                }else{
                    cmdBuf[bufLen++] = sData[i];
                    rcv_state = PHY_R_NORMAL_STATE;
                }
                break;
            }
        }
    }

    /*BX_printf("\n---\n---\n");
    BX_printf("in protocol_phy::data_transf_meaning...\n");
    for(i = 0; i < bufLen; i++) {
        BX_printf("%d=%02x ",i,cmdBuf[i]);
    }BX_printf("\n---\n---\n");*/



    return bufLen;
}

// 数据反转义
Ouint32 message_deal::data_re_transf_meaning(Ouint8 *sData, Ouint8 *cmdBuf,Ouint32 len,Ouint8 *frame_status)
{

    Oint32 i = 0;
    Ouint32 bufLen = 0;
   /* if(sData.len > PHY_DATA_LEN) {
        return 0;
    }*/

    send_state = PHY_S_FIRST_STATE;
    *frame_status = 0;
    bufLen = 0;

    /*BX_printf("\n---\n---\n");
    BX_printf("in protocol_phy::data_re_transf_meaning src...\n");
    for(i = 0; i < len; i++) {
        BX_printf("%d=%02x ",i,cmdBuf[i]);
    }BX_printf("\n---\n---\n");*/

    if(send_state == PHY_S_FIRST_STATE){
        bufLen = 0;
        // sData[bufLen++] = PHY_HEAD_VALUE ;
        // sData[bufLen++] = PHY_HEAD_VALUE ;
        // sData[bufLen++] = PHY_HEAD_VALUE ;
        send_state = PHY_S_PROCEED_STATE;
        *frame_status = 0;
    }

    for(i = 0 ;i < len ;i++) {
        /*if(send_state == PHY_S_FIRST_STATE){
            bufLen = 0;
            BX_printf("%d=",bufLen);
            sData[bufLen++] = PHY_HEAD_VALUE ;
            BX_printf("%02x ,i=%02x ",PHY_HEAD_VALUE,i);
            send_state = PHY_S_PROCEED_STATE;
            *frame_status = 0;
        }else */if(send_state == PHY_S_PROCEED_STATE){
            switch (cmdBuf[i]) {
            case PHY_HEAD_VALUE:
                sData[bufLen++] = PHY_TRANSFER_start_VALUE;
                sData[bufLen++] = PHY_TRANSFER_FLAG0;
                send_state = PHY_S_PROCEED_STATE;//PHY_S_TRANSFER_STATE1;
                break;

            case PHY_TRANSFER_start_VALUE://0xa6
                sData[bufLen++] = PHY_TRANSFER_start_VALUE;
                sData[bufLen++] = PHY_TRANSFER_FLAG1;
                send_state = PHY_S_PROCEED_STATE;//PHY_S_TRANSFER_STATE2;
                break;

            case PHY_TRAIL_VALUE:
                sData[bufLen++] = PHY_TRANSFER_end_VALUE;
                sData[bufLen++] = PHY_TRANSFER_FLAG0;
                send_state = PHY_S_PROCEED_STATE;//PHY_S_TRANSFER_STATE3;
                break;

            case PHY_TRANSFER_end_VALUE:
                sData[bufLen++] = PHY_TRANSFER_end_VALUE;
                sData[bufLen++] = PHY_TRANSFER_FLAG1;
                send_state = PHY_S_PROCEED_STATE;//PHY_S_TRANSFER_STATE4;
                break;

            default: 
                sData[bufLen++] = cmdBuf[i];
                send_state = PHY_S_PROCEED_STATE;
                break;
            }
        }else{
            switch (send_state) {
            case PHY_S_TRANSFER_STATE1:
            case PHY_S_TRANSFER_STATE3:
                sData[bufLen++] = PHY_TRANSFER_FLAG0;
                send_state = PHY_S_PROCEED_STATE;
                break;

            case PHY_S_TRANSFER_STATE2:
            case PHY_S_TRANSFER_STATE4:
                sData[bufLen++] = PHY_TRANSFER_FLAG1;
                send_state = PHY_S_PROCEED_STATE;
                break;
            default:
                break;
            }
        }
    }
    // add 0x5a
    // sData[bufLen++] = PHY_TRAIL_VALUE;
//    BX_printf("\n---\n---\n");
//    BX_printf("in protocol_phy::data_re_transf_meaning...\n");
//    for(i = 0; i < bufLen; i++) {
//        BX_printf("%d=%02x ",i,sData[i]);
//    }BX_printf("\n---\n---\n");
    return bufLen;
}

/*
 * @param :cmdBuf(head)(swap)
 * @return
 */
void message_deal::swap_phy_head(Ouint8 *cmdBuf)
{
    /*BX_printf("\n---\n---\n");
    BX_printf("in protocol_phy::swap_phy_head...\n");

    BX_printf("cmdBuf[0]=%02x , cmdBuf[1] = %02x ",cmdBuf[0],cmdBuf[1]);
    BX_printf("\n---\n---\n");*/


    Ouint16 temp = ((PhyData_Type *)cmdBuf)->dstAddr;

    ((PhyData_Type *)cmdBuf)->dstAddr = ((PhyData_Type *)cmdBuf)->srcAdd;

    /*BX_printf("\n---\n---\n");
    BX_printf("in protocol_phy::swap_phy_head...\n");

    BX_printf("dstAddr=%02x ",((PhyData_Type *)cmdBuf)->dstAddr);
    BX_printf("\n---\n---\n");*/

    ((PhyData_Type *)cmdBuf)->srcAdd = temp;

    /*BX_printf("\n---\n---\n");
    BX_printf("in protocol_phy::swap_phy_head...\n");

    BX_printf("srcAdd=%02x ,temp=%02x ",((PhyData_Type *)cmdBuf)->srcAdd ,temp);
    BX_printf("\n---\n---\n");*/

}

